PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 364

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
XFERE
ABRTE
MAXLE
MINLE
LCDV
OCDV
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the RCFP performance monitor counter holding
registers. When XFERE is set to logic 1, the interrupt is enabled.
The Abort Packet Enable bit enables the generation of an interrupt due to the reception of an
aborted packet. When ABRTE is set to logic 1, the interrupt is enabled.
The Maximum Length Packet Enable bit enables the generation of an interrupt due to the
reception of a packet exceeding the programmable maximum packet length. When MAXLE
is set to logic 1, the interrupt is enabled.
The Minimum Length Packet Enable bit enables the generation of an interrupt due to the
reception of a packet that is smaller than the programmable minimum packet length. When
MINLE is set to logic 1, the interrupt is enabled.
The LCDV bit gives the ATM Loss of Cell Delineation state. When LCDV is logic 1, an out
of cell delineation (LCD) defect has persisted for the number of cells specified in the LCD
Count Threshold register. When LCDV is logic 0, the RCFP has been in cell delineation for
the number of cells specified in the RCFP LCD Count Threshold register. The cell time
period can be varied by using the LCDC[10:0] register bits in the RCFP LCD Count
Threshold register.
The OCDV bit indicates the ATM cell delineation or packet out of frame alignment state.
When OCDV is logic 1, the cell delineation state machine is in the 'HUNT' or 'PRESYNC'
states and is hunting for the cell boundaries or the packet processor is in out of frame
alignment. When OCDV is logic 0, the cell delineation state machine is in the 'SYNC' state
and cells are passed through the receive FIFO, or the packet processor is in frame alignment.
S/UNI-2488 Telecom Standard Product Datasheet
Released
364

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