PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 365

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0742H: RCFP Interrupt Indication and Status
LCDI
OCDI
CRCI
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The LCDI bit is set to logic 1 when there is a change in the loss of cell delineation (LCD)
state. The current value of the LCD state is available through the LCDV bit in the RCFP
Interrupt Enable and Status register (0x0741). This interrupt can be masked using LCDE. If
WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set
to logic 0, then a read of this register automatically clears the bit.
The OCDI bit is set to logic 1 when the RCFP ATM cell processor enters or exits the SYNC
state or the packet processor enters or exits the frame alignment state. This interrupt can be
masked using OCDE. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this
bit. If WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
The CRCI bit is set to logic 1 when an ATM HCS or packet FCS error is detected. This
interrupt can be masked using CRCE. If WCIMODE is set to logic 1, only over-writing with
a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read of this register automatically
clears the bit.
Type
R
R
R
R
R
R
R
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
MINLI
MAXLI
ABRTI
XFERI
Reserved
CRCI
OCDI
LCDI
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
365