PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 374

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 074CH: RCFP Receive Erroneous FCS/HCS Counter
EFCS[15:0]
EHCS[7:0]
A write to any one of the RCFP performance monitor registers loads the registers with the current
counter value and resets the internal counters to 1 or 0. The counter reset value is dependent on if
there was a count event during the transfer of the count to these Counter registers. The counter
should be polled regularly to avoid saturation.
To allow for synchronization update with all other blocks, writing to register 0000H will initiate a
global performance counter update.
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
When POS mode is selected, the EFCS[15:0] bits indicate the number of received FCS errors
during the last accumulation interval. The FCS calculation will proceed independent of any
errors detected upstream. Thus, under abort, max length violations, etc, one might get FCS
violations as well.
When ATM mode is selected, the EHCS[7:0] bits indicate the number of HCS errors received
in the last accumulation interval.
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
EFCS[15]
EFCS[14]
EFCS[13]
EFCS[12]
EFCS[11]
EFCS[10]
EFCS[9]
EFCS[8]
EFCS[7]/EHCS[7]
EFCS[6]/EHCS[6]
EFCS[5]/EHCS[5]
EFCS[4]/EHCS[4]
EFCS[3]/EHCS[3]
EFCS[2]/EHCS[2]
EFCS[1]/EHCS[1]
EFCS[0]/EHCS[0]
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
374