PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 380

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
DELINDIS
XFERE
FIFO_UDRE
FIFO_ERRE
The DELINDIS (POS delineation control bit) enables the carriage of unmodified POS traffic.
In POS mode, flags are not inserted (unless in FIFO underrun) and stuffing is disabled. FCS
insertion and scrambling are still controlled by CRC_SEL and SCRMBL.
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the transmitted packet/cell counter, transmitted byte
counter, and aborted packet counter holding registers. When XFERE is set to logic 1, the
interrupt is enabled.
The FIFO_UDRE bit enables the generation of an interrupt due to a FIFO underrun. When
FIFO_UDRE is set to logic 1, the interrupt is enabled and the INTB signal will be set to
logic 0 whenever FIFO_UNRI is set to logic 1.
The FIFO_ERRE bit enables the generation of an interrupt due to a FIFO error. When
FIFO_ERRE is set to logic 1, the interrupt is enabled and the INTB signal will be set to logic
0 whenever FIFO_ERRI is set to logic 1.
S/UNI-2488 Telecom Standard Product Datasheet
Released
380