PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 381

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0751H: TCFP Interrupt Indication
XFERI
FIFO_UDRI
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The XFERI bit indicates that a transfer of accumulated counter data has occurred. A logic 1 in
this bit position indicates that the transmitted cell/packet counter, transmitted byte counter,
and aborted packet counter holding registers have been updated. This update is initiated by
writing to one of the TCFP counter register locations, or initiating a global performance
monitor update by writing to register 0000H. XFERI is set to logic 0 when this register is
read. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If
WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
The FIFO_UDRI bit is set high when an attempt is made to read from the FIFO while it is
empty. This is considered a system error. The FIFO_UDRI bit is set to logic 0 immediately
after a read to this register. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears
this bit. If WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
Type
R
R
R
Function
FIFO_ERRI
FIFO_UDRI
XFERI
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
381