PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 382

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
FIFO_ERRI
This bit is set to one when an error is detected on the read side of the FIFO. An error can be
caused by an abnormal sequence of TSOP and TEOP signals or the assertion of FIFO_ERR.
Such errors are normally caused by a previous FIFO overrun or underrun condition or a user
asserted error from the POS-PHY L3 interface. The FIFO_ERRI bit is reset immediately
after a read to this register. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears
this bit. If WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
S/UNI-2488 Telecom Standard Product Datasheet
Released
382

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