PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 430

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0790H: SIRP Configuration Timeslot
All Reserved bits must be set to their default values for proper operation.
TS1_PROV
TS1_ERDI
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 15 SIRP RDI Settings
TS1_PROV suppresses the flow of data through the SIRP. For proper operation of the S/UNI
2488, the TS1_PROV must be set to 1 except when TPAIS_EN (bit 3 register 0002H) is
asserted. TS1_PROV should be set to logic 0 only when transmit path AIS is to be generated.
The TS1_ERDI bit selects between normal and extended RDI encoding. When TS1_ERDI is
set high, extended RDI is selected. When TS1_ERDI is set low, normal RDI is selected.
These selections are summarized in Table 15. Table 15 SIRP RDI Settings
TS1_ERDI = 1
TS1 ERDI = 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ERDI Code
001
010
101
110
000
000
Unused
Unused
Unused
Unused
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TS1_FORCE_LCD
TS1_RDI20F
TS1_ERDI
Reserved
Reserved
TS1_PROV
Function
ERDI Interpretation
No RDI-P defect
ERDI-P payload defect
ERDI-P server defect
ERDI-P connectivity defect
No RDI-P defect
No RDI-P defect
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
0
0
0
0
0
0
0
0
0
1
1
0
Released
430

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