PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 432

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 079CH: SIRP Configuration
LCD[1:0]
RDIPRIMID[1:0]
RDIPRIHI[1:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The LCD[1:0] bits represent the top two bits of the RDI code generated when a Loss of ATM
Cell Delineation (LCD) event is detected. The third bit (LSB) is the inverse of the second
(LCD[0]). To conform to Bellcore and ITU SONET/SDH standards, this register field
must be set to 01 (note the default is 10).
The RDIPRIMID[1:0] bits specify which two-bit alarm code point (RDI) will be treated as
the second highest priority code. These bits combined with the RDIPRIHI bits determine the
priority scheme. The bits are interpreted as shown in RDIPRIHI[1:0]. To comply with
Bellcore and ITU SONET/SDH standards this register field must be set to 11.
The RDIPRIHI[1:0] bits specify which two-bit alarm code point (RDI) will be treated as the
highest priority code. High priority codes will replace low priority codes at the next transmit
G1 byte, instead of allowing 10/20 copies to be sent. The highest priority alarm is sent 10/20
times before replacement is allowed. To comply with Bellcore and ITU SONET/SDH
standards this register field must be set to 10.
Type
R/W
R/W
R/W
R/W
R/W
R/W
Unused
Unused
Unused
Unused
Unused
Unused
RDIPRIHI[1]
RDIPRIHI[0]
RDIPRIMID[1]
RDIPRIMID[0]
LCD[1]
LCD[0]
Function
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
0
Released
432