PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 439

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0804H: PRGM Monitor Byte Error Interrupt Status
Register 0814H: PRGM Aux 2 Monitor Byte Error Interrupt Status
Register 0824H: PRGM Aux 3 Monitor Byte Error Interrupt Status
Register 0834H: PRGM Aux 4 Monitor Byte Error Interrupt Status
MONx_ERRI
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Monitor Byte Error Interrupt Status registers contain the status of the interrupt generated
by each of the 48 STS-1 paths when an error has been detected.
PRGM Monitor Byte Error Interrupt Status register, N = 0.
PRGM Aux2 Monitor Byte Error Interrupt Status register, N = 1.
PRGM Aux3 Monitor Byte Error Interrupt Status register, N = 2.
PRGM Aux4 Monitor Byte Error Interrupt Status register, N = 3.
The MONx_ERRI bit is set high when the monitor is in the synchronized state and when an
error in a PRBS byte is detected in the STS-1 path x. This bit is independent of
MONx_ERRE, and is cleared after it has been read. MONx_ERRI is cleared to logic 0 when
this register is read if WCIMODE is set to logic 0. MONx_ERRI is cleared only when it is
written to logic 1 if WCIMODE is set to logic 1.
Type
R
R
R
R
R
R
R
R
R
R
R
R
Unused
Unused
Unused
Unused
MON[N+12]_ERRI
MON[N+11]_ERRI
MON[N+10]_ERRI
MON[N+9]_ERRI
MON[N+8]_ERRI
MON[N+7]_ERRI
MON[N+6]_ERRI
MON[N+5]_ERRI
MON[N+4]_ERRI
MON[N+3]_ERRI
MON[N+2]_ERRI
MON[N+1]_ERRI
Function
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
Released
439