PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 442

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
MONx_SYNCI
The Monitor Synchronization Interrupt Status registers indicate synchronization interrupts for
each of the 48 STS-1 paths.
PRGM Monitor Synchronization Interrupt Status register, N = 0.
PRGM Aux2 Monitor Synchronization Interrupt Status register, N = 1.
PRGM Aux3 Monitor Synchronization Interrupt Status register, N = 2.
PRGM Aux4 Monitor Synchronization Interrupt Status register, N = 3.
The Monitor Synchronization Interrupt Status Interrupt (MONx_SYNCI) bit is set high when
a change occurs in the monitor’s synchronization status. Whenever a state machine of the x
STS-1 path goes from Synchronized to Out Of Synchronization state or vice-versa, the
MONx_SYNCI is set high. For concatenated payloads, only the STS-1 path state machine
that first detects the change in Synchronization Status in this PRBS monitor will set
MONx_SYNCI high. This bit is independent of MONx_SYNCE. If WCIMODE is set to
logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read
of this register automatically clears the bit.
Note that the PRGM will synchronize on an all zeroes or all ones pattern. To verify that a
valid PRBS pattern is the signal the PRGM is locked to, check the PRBS[22:0] bits in the
PRGM Monitor PRBS Accumulator Page. If the bits are not all zeroes or all ones, then the
synchronization is due to locking on a valid PRBS pattern.
S/UNI-2488 Telecom Standard Product Datasheet
Released
442