PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 446

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Indirect Register 00H: PRGM Monitor Timeslot Configuration Page
All Reserved bits must be set to their default values for proper operation.
MON_ENA
INV_PRBS
RESYNC
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Monitor Enable register bit enables the PRBS monitors for the PRGM blocks (all 48). If
MON_ENA is set high, a PRBS sequence is generated and compared to the incoming PRBS
sequence inserted in the payload of the SONET/SDH frame. If MON_ENA is low, the input
monitor data is ignored.
INV_PRBS sets the monitor to invert the PRBS before comparing it to the internally
generated payload. When set high, the PRBS bytes will be inverted. When set low, the
PRBS bytes will be compared unmodified.
RESYNCH sets the monitor to re-initialize the PRBS sequence. When set high, the monitor’s
state machines will be forced in the Out Of Sync state and will automatically try to
resynchronize to the incoming stream. To force another resynchronization, the bit needs to be
set low again before it is set high.
Type
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
Unused
Unused
Unused
Unused
Unused
Reserved
Reserved
SEQ_PRBSB
Reserved
RESYNC
INV_PRBS
Reserved
MON_ENA
Function
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
0
0
X
X
0
0
X
0
0
0
0
Released
446