PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 450

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Indirect Register 08H: PRGM Generator Timeslot Configuration Page
All Reserved bits must be set to their default values for proper operation.
INV_PRBS
FORCE_ERR
SEQ_PRBSB
S[1:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INV_PRBS sets the generator to invert the PRBS before inserting it in the payload. When set
high, the PRBS bytes will be inverted. When set low, the PRBS bytes will be inserted
unmodified.
The Force Error bit is used to force bit errors in the inserted pattern. When set high, the MSB
of the next byte will be inverted, inducing a single bit error. The register will clear itself
when the operation is complete. A read operation will always result in a logic ‘0’.
SEQ_PRBSB enables the insertion of a PRBS sequence or a sequential pattern in the payload.
When low, the payload is filled with PRBS bytes. When high, a sequential pattern is inserted.
The S[1:0] bits contain the value inserted in the S[1:0] bit positions in the payload pointer.
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
Unused
Unused
Reserved
PRBS_ENA
Unused
Unused
Reserved
Reserved
S[1]
S[0]
SEQ_PRBSB
Reserved
FORCE_ERR
INV_PRBS
Reserved
Function
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
0
0
X
X
0
0
0
0
0
0
0
X
0
0
Released
450