PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 463

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0860H: T8TE APS1 Control and Status
Register 0868H: T8TE APS2 Control and Status
Register 0870H: T8TE APS3 Control and Status
Register 0878H: T8TE APS4 Control and Status
The Reserved bit must be set to its default value for proper operation.
DLCV
CENTER
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The diagnose line code violation bit (DLCV) controls the insertion of line code violation in
the APS outgoing serial data. When DLCV is set high, the encoded data is continuously
inverted to generate line code violations. The inverted data will represent both valid and
invalid 8B/10B characters as not all 8B/10B characters have positive running disparity and
negative running disparity characters simply the inverse of each other. Note that Serial-
TelecomBus control characters are not affected by the DLCV bit and are passed unaltered.
The FIFO centering control bit (CENTER) controls the separation of the FIFO read and write
pointers. CENTER is a write only bit. When a logic high is written to CENTER, and the
current FIFO depth is not in the range of 3, 4 or 5 characters, the FIFO depth is forced to be
four 8B/10B characters deep with a momentary data corruption. Writing to the CENTER bit
when the FIFO depth is in the 3, 4 or 5 character range produces no effect. CENTER always
returns a logic low when read.
Type
R/W
R/W
R/W
W
R/W
R/W
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
FIFOERRE
TPINS
LLBEN
CENTER
DLCV
Function
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
Released
463