PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 469

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0865H: T8TE APS1 Analog Control
Register 086DH: T8TE APS2 Analog Control
Register 0875H: T8TE APS3 Analog Control
Register 087DH: T8TE APS4 Analog Control
All Reserved bits must be set to their default values for proper operation.
ARSTB
APISO_ATMSB
TXLV_ATMSB
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The analog reset bit (ARSTB) controls the TXLV and APISO operation. When ARSTB is set
low, the TXLV and APISO are reset. This bit must be set to logic 1 for normal operation.
ARSTB should be set to logic 0 to conserve power consumption for applications not using the
APS port.
The APISO analog test mode select bit (APISO_ATMSB) controls the APISO test operation.
APISO_ATMSB drives the output APISO_ATMSB pin low to enable test mode in the
APISO. This bit must be set to logic 1 for normal operation.
The TXLV analog test mode select bit (TXLV_ATMSB) controls the TXLV test operation.
TXLV_ATMSB drives the output TXLV_ATMSB pin low to enable test mode in the TXLV
block. This bit must be set to logic 1 for normal operation.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unused
Unused
Unused
Unused
Reserved
Reserved
IDDQ
TXLV_ENB
APISO_ENB
ATIN[3]
ATIN[2]
ATIN[1]
ATIN[0]
TXLV_ATMSB
APISO_ATMSB
ARSTB
Function
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
0
0
0
0
0
0
0
0
0
1
1
1
Released
469