PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 473

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
ERRORE
OVERRIDE
The ERROR interrupt enable (ERRORE) bit enables the error indication interrupt. When
ERRORE is set high, an interrupt is generated upon assertion event of the ERR output and
ERROR register. When ERRORE is set low, changes in the ERROR and ERR status do not
generate an interrupt.
The override control (OVERRIDE) disables the DLL operation. When OVERRIDE is set
low, the DLL generates the DLLCLK by delaying the RFCLK until the rising edge of the
feedback clock occurs at the same time as the rising edge of RFCLK. When OVERRIDE is
set high, the DLLCLK output is a buffered version of the RFCLK input. This bit must be set
to logic 0 for normal operation.
S/UNI-2488 Telecom Standard Product Datasheet
Released
473