PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 475

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0882H: RXDLL Delay Tap Status/DLL Reset
The DLL Delay Tap Status Register indicates the delay tap used by the DLL to generate the
outgoing clock.
Writing to this register performs a software reset of the DLL. A software reset requires a
maximum of 24*256 RFCLK cycles for the DLL to regain lock. During this time the DLLCLK
phase is adjusting from its current position to delay tap 0 and back to a lock position.
TAP[7:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The tap status register bits (TAP[7:0]) specifies the delay line tap the DLL is using to
generate the outgoing clock DLLCLK.
When TAP[7:0] is logic zero, the DLL is using the delay line tap with minimum phase delay.
When TAP[7:0] is equal to 255, the DLL is using the delay line tap with maximum phase
delay. TAP[7:0] is invalid when vernier enable VERN_EN is set to one.
These bits are not used in normal operation.
Type
R
R
R
R
R
R
R
R
Unused
Unused
Unused
Unused
Unused
Unused
TAP[7]
TAP[6]
TAP[5]
TAP[4]
TAP[3]
TAP[2]
TAP[1]
TAP[0]
Function
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
Released
475