PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 476

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0883H: RXDLL Control Status
The DLL Control Status Register provides information of the DLL operation.
RUN
CHANGE
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The DLL lock status register bit (RUN) indicates the DLL found a delay line tap in which the
phase difference between the rising edge of the feedback clock and the rising edge of RFCLK
is zero. After system reset, RUN is logic zero until the phase detector indicates an initial lock
condition. When the phase detector indicates lock, RUN is set to logic 1.
The RUN register bit is cleared only by a system reset or a software reset (via register bits in
register 2). RUN is forced high when the OVERRIDE register is set high or when the
VERN_EN register is set high.
The delay line tap change register bit (CHANGE) indicates the DLL has moved to a new
delay line tap. CHANGE is set high for eight RFCLK cycles when the DLL moves to a new
delay line tap.
This bit is not used in normal operation.
Type
R
R
R
R
R
R
R
Unused
Unused
Unused
Unused
Unused
Unused
RFCLKI
FBCLKI
ERRORI
CHANGEI
ERROR
CHANGE
RUN
Function
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
0
X
Released
476