PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 478

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
FBCLKI
RFCLKI
The feedback clock event register bit FBCLKI provides a method to monitor activity on the
feedback clock. When the feedback clock primary input changes from a logic zero to a logic
one, the FBCLKI register bit is set to logic one.
When WCIMODE is low, the FBCLKI register bit is cleared immediately after it is read, thus
acknowledging the event has been recorded. When WCIMODE is high, the FBCLKI register
bit is cleared immediately after a logic one is written to the FBCLKI register, thus
acknowledging the event has been recorded.
This bit is not used in normal operation.
The system clock event register bit RFLCKI provides a method to monitor activity on the
system clock. When the RFCLK primary input changes from a logic zero to a logic one, the
RFCLKI register bit is set to logic one. The RFCLKI register bit is cleared immediately after
it is read, thus acknowledging the event has been recorded.
When WCIMODE is low, the RFCLKI register bit is cleared immediately after it is read, thus
acknowledging the event has been recorded. When WCIMODE is high, the RFCLKI register
bit is cleared immediately after a logic one is written to the RFCLKI register, thus
acknowledging the event has been recorded.
S/UNI-2488 Telecom Standard Product Datasheet
Released
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