PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 493

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
RXAPS_NDF_EN
RXAPS_PAIS_EN
RXAPS_LINK_PAIS
TLREIINS
Reserved
The RXAPS_NDF_EN bit is used to enable generation of an NDF frame when the AIS
declaration described in the RXAPS_PAIS_EN bit description clears. When
RXAPS_NDF_EN is logic 1, an NDF frame is generated when the AIS condition is cleared.
When RXAPS_NDF_EN is logic 0, no NDF frame is generated when the AIS condition is
cleared.
The RXAPS_PAIS_EN bit is used to enable the AIS generation when the receive APS J0
character is decoded as all 1’s, the 8B/10B encoded PAIS signal is detected, or when loss of
J0 alignment, or loss of character alignment is declared by the APS receiver (R8TD), When
RXAPS_PAIS_EN is logic 1, the feature is enabled. When RXAPS_PAIS_EN is logic 0, the
feature is disabled.
Note that the assertion of AIS for this feature is based on the J0 character being decoded as all
1’s. This occurs through the detection of the 8B/10B AIS character, by normal decode of the
8B/10B encoded character for 0xFF, or the assertion of loss-of-character alignment or loss-of-
J0 alignment by the APS receiver R8TD. Once the J0 character is not decoded as all 1’s, then
AIS is deasserted.
The RXAPS_LINK_PAIS is used to configure the four Rx APS link AIS indications as 4
separate STS-12/STM-4 channel or as one STS-48/STM-16 channel. When
RXAPS_LINK_PAIS is set to logic 1, the 4 APS links are treated as one STS-48/STM-16
channel. If any one of the APS links loses J0 alignment, character alignment, or detects AIS,
then data from all four links will be forced to AIS state. When RXAPS_LINK_PAIS is set to
logic 0, the 4 APS links are treated separately.
The TLREIINS register bit controls the insertion of the line remote error indication into the
data stream. When TLREIINS is set to logic 1, the remote errors detected by the RRMP are
inserted in the M1 byte of STS-1/STM-0 #3 according to the priority of Table 4. When
TLREIINS is set to logic 0, the REI in the M1 byte is set to 0.
The Reserved bit must be set to logic 0 for proper operation.
S/UNI-2488 Telecom Standard Product Datasheet
Released
493