PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 522

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Path Overhead Bytes
The Path Overhead (POH) contains each of the bytes mentioned in this section. POH can be
extracted and inserted via the RPOH and TPOH ports respectively. Note that only the first STS-
12 can be accessed in this manner. This is wholly sufficient for OC-48c as there is only one POH
and it occurs in the first STS-1. Some POH bytes cannot be extracted for some configurations in
cross-connect mode. No POH can be inserted in cross-connect mode. See also the description of
POH Insertion and Extraction in the Functional Timing section of this document.
POH can also be inserted by the THPP via register writes. See the THPP description in the
Functional Description chapter. The POH should always be configured either via the TPOH port
or by the insertion registers within the THPP.
The POH consists of the following bytes:
·
In the transmit direction, characters can be inserted using the TTTP Path Trace register. The
register is the default selection and resets to 0x00 to enable the transmission of NULL characters
from a reset state.
In the receive direction, the path trace message is optionally extracted into the 16 or 64 byte path
trace message buffer.
·
In the transmit direction, the S/UNI-2488 calculates the B3 bytes. The calculated code is then
placed in the next frame.
In the receive direction, the S/UNI-2488 calculates the B3 code and compares this calculation
with the B3 byte received in the next frame. B3 errors are accumulated in an error event counter.
·
·
In the transmit direction, the S/UNI-2488 provides register bits to control the path RDI (bit 5) and
auxiliary path RDI (bit 6) states. For path RDI, the number of B3 errors detected in the previous
interval is inserted either automatically or using a register. This path RDI code has 9 legal values,
namely 0 to 8 errors.
In the receive direction, a legal path RDI value is accumulated in the path RDI event counter. In
addition, the path RDI and auxiliary path RDI signal states are available in internal registers.
J1: The Path Trace byte is used to repetitively transmit a 64-byte CLLI message (for SONET
networks), or a 16-byte E.164 address (for SDH networks). When not used, this byte should
be set to transmit continuous null characters. Null is defined as the ASCII code, 0x00.
B3: The path bit interleaved parity byte provides a path error monitoring function.
C2: The path signal label indicator identifies the equipped payload type. For ATM payloads,
the identification code is 0x13. For Packet over SONET (including X
scrambling), the identification code is 0x16.
G1: The path status byte provides a path RDI function, and a path remote defect indication
function. Three bits are allocated for remote defect indications: bit 5 (the path RDI bit), bit 6
(the auxiliary path RDI bit) and bit 7 (Enhanced RDI bit). Taken together these bits provide a
eight state path RDI code that can be used to categorize path defect indications.
S/UNI-2488 Telecom Standard Product Datasheet
43
+1 payload
Released
522