PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 525

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.6
13.7
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
TXSDQ and RXSDQ “Block” Sub-Units
The TXSDQ and RXSDQ FIFOs each have a maximum capacity of 3072 bytes. However, the
FIFO is divided up into 192 sub-units called blocks. Each block is 16 bytes in size and is the
smallest resolution discernable by the TXSDQ and RXSDQ. This means that a packet fragment
smaller than 16-bytes and ending with an EOP will use up an entire block. For example, a 17-
byte packet will use up two blocks even though the 2nd block is only 1/16th occupied. The
remaining 15/16th cannot be used by another packet and is wasted. A 32-byte packet will also
use up two blocks, but this time, none of the FIFO capacity is wasted. A 72-byte packet will use
up five blocks. The first four blocks will each be fully utilized. The remaining 8 bytes will fill
half of the remaining block. The other half of that block is wasted.
TXSDQ Buffer Available Operation
For the FIFO configured in the TXSDQ, a Buffer Available (BA) bit indicates whether on not the
FIFO can accept more data. The BA status is given (BA = 1) when the TXSDQ can
accommodate at least another injection of BT[4:0] + 1 blocks (block = 16 bytes) into its FIFO.
When the number of blocks available in the FIFO is less than (BT[4:0] + 1), then BA is
deasserted (BA = 0). At this point, no more new data can be accepted, but the current transaction
completes (if BT is not set at the maximum for the FIFO). Eventually, when some of the data in
the FIFO is drained by the read interface, the available FIFO space will equal or exceed BT[4:0]
+ 1. BA is asserted when this condition is reached. The BA state is reflected by the TCA and
DTPA output signals on the Utopia L3 and POS-PHY L3 interfaces when the PHY is selected
and/or polled.
In setting the TXSDQ buffer available threshold BT[4:0], the maximum data burst size from the
upstream device must be taken into account. Section 13.12 describes how to program BT[4:0] to
keep the upstream device from overflowing the TXSDQ FIFO. In general, the following formula
applies:
(BT[4:0] + 1) ³ max burst size from upstream device + system application margin
The values of BT[4:0] and DT[7:0] in the TXSDQ Indirect Data and Buffer Available Thresholds
register must be set so that:
(DT[7:0] + 1) + (BT[4:0] + 1) ≤ FIFO size
The FIFO size is set using the FIFO_BS[1:0] register bits in the TXSDQ FIFO Indirect
Configuration register and DT[7:0] is the TXSDQ is set in the TXSDQ Indirect Data and Buffer
Available Thresholds register. This constraint keeps the FIFO from entering a state where the
TXSDQ cannot sustain a new burst from the upstream device and the downstream TCFP block
does not have enough data to initiate a transfer.
For UL3 ATM FIFOs, BT[4:0] and DT[7:0] must be set equal to the value 3. This sets the
threshold to be 4 blocks which is the space occupied by an ATM cell.
S/UNI-2488 Telecom Standard Product Datasheet
Released
525