PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 533

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.13 System Interface Error Recovery
13.13.1 Utopia Level 3 Transmit Interface Misalignment Recovery
13.13.2 Utopia Level 3 Receive Interface Misalignment Recovery
13.13.3 Utopia Level 3 Transmit Clock (TFCLK) Error Recovery
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
On the Transmit UL3 interface, cell alignment is done on logic 1-to-0 transition of TENB. That
is, TSOC is expected on the same cycle where TENB has just transitioned to logic 0. Thus, if the
upstream device has misalignment between its TENB and TSOC, the S/UNI-2488 will align its
cells to the TENB and may give error indications on its RUNTCELLI (TXPHY Interrupt Status
register, 789H) and/or SOPI interrupt (TXSDQ SOP Error Port and Interrupt Indication, 775H).
Once the upstream device has realigned its signals, the S/UNI-2488 will realign on the next 1-to-0
transition of TENB.
On the Receive UL3 interface, cell transfer is aligned to the RENB signal. Once asserted to logic
0, RENB must not deassert until cycle P11 of a cell. The S/UNI-2488 will not respond to early
deassertions of RENB and will continue transfer of the cell in progress.
To realign the S/UNI-2488 to the downstream device, the RENB must remain deasserted for more
than 13 clock cycles. This will guarantee that the S/UNI-2488 has completed transfer of any cell
and the next cell will be aligned to RENB.
This means that RENB cannot be tied low with the downstream device expecting to align using
the RSOC output of the S/UNI-2488.
The alternate method to realign cells is to unprovision the RCFP and then unprovision and flush
the RXSDQ. When the RXSDQ and RCFP are restarted, the cells will be properly aligned to
RENB.
When the TFCLK is taken away and restored or is corrupted by a glitch in UL3 mode, the TxDLL
will indicate an error by asserting the ERRORI register bit in the TxDLL Control Status register.
The SUNI 2488 may also generate continuous SOPI interrupts in the TXSDQ block or
RUNTCELLI interrupts in the TXPHY block which indicate a misalignment state.
When this condition is detected, the following recovery procedure should be used:
1. Detect TxDLL ERRORI interrupt
2. Reset the TxDLL by writing to the TxDLL Delay Tap Status register (0886H)
3. Unprovision and flush the TXSDQ to stop the upstream device from transmitting (indirect
4. Reset the TXPHY
5. Clear the reset on the TXPHY
register 0779H, bit 15 and indirect register 0778H, bit 13)
S/UNI-2488 Telecom Standard Product Datasheet
Released
533