PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 534

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.13.4 Utopia Level 3 Receive Clock (RFCLK) Error Recover
13.13.5 POS-PHY Level 3 Transmit (TFCLK) Error Recovery
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
6. Clear the flush bit and provision the TXSDQ
When the RFCLK is taken away and restored or is corrupted by a glitch in UL3 mode, the SUNI-
2488’s RxDLL will indicate an ERRORI interrupt. The system-side link-layer device may get
continuous RSOC errors and the RXPHY block may give continuous RUNTCELLI interrupts.
When this condition is detected, the following recovery procedure should be used:
1. Detect RxDLL ERRORI interrupt
2. Reset the RFCLK_DLL by writing to the RxDLL Delay Tap Status register (0882H)
3. Unprovision the RCFP cell/packet processors (register 0740H bit 0)
4. Unprovision and flush the RXSDQ (indirect register 0769H, bit 15 and indirect register
5. Reset the RXPHY
6. Clear the reset on the RXPHY
7. Clear the flush bit and provision the RXSDQ
8. Provision the RCFP
When the TFCLK is taken away and restored or corrupted by a glitch in PL3 mode, the TxDLL
will indicate an ERRORI interrupt. In some cases the SUNI-2488 TXSDQ also asserts SOPI, and
EOPI interrupts.
1. Detect ERRORI interrupt in TXDLL Control Status Register (register 0887H)
2. Reset the TxDLL (write to register 0886H)
3. Disable the TXSDQ FIFO (indirect register 0779H, bit 15)
4. Flush the TXSDQ FIFO (indirect register 0778H, bit 13)
5. Reset the TXPHY
6. Clear the reset on the TXPHY
7. Enable the TXSDQ (indirect register 0779H, bit 15)
When this condition is detected, the following recovery procedure should be used:
0768H, bit 13)
S/UNI-2488 Telecom Standard Product Datasheet
Released
534