PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 536

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.15 Using the PRBS Generator and Monitor (PRGM)
13.15.1 Synchronization
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Normal Error Reporting Mode (TS1_RMODE[1:0] =b’11)
In this mode, the REI and RDI values are sourced from the remote alarm port. If the extended
RDI mode is enabled, the receive cell processor’s loss-of-cell delineation state, which is mapped
to a programmable RDI code if asserted, is compared with the remote port’s RDI code. The
higher priority RDI will take precedence.
A pseudo-random (using the X
inserted/extracted in the SONET/SDH payload. It cannot be inserted into the ATM cell or packet
payload. With PRBS data and incrementing data patterns, the payload envelope is filled with
pseudo-random/incrementing bytes with the exception of POH and fixed stuff columns. In the
case of the incrementing counts, the count starts at 0 and increments to FFh before the count starts
over at 0 once again. The incrementing count is free to float within the payload envelope and
therefore the 0 count is not associated with any fixed location within a payload envelope.
Before being able to monitor the correctness of the PRBS payload, the monitor must synchronize
to the incoming PRBS. The process of synchronization involves synchronizing the monitoring
LFSR to the transmitting LFSR. Once the two are synchronized the monitoring LFSR is able to
generate the next expected PRBS bytes. When receiving sequential PRBS bytes (STS-12c/VC-4-
4c), the LFSR state is determined after receiving 3 PRBS bytes (24 bits of the sequence). The last
23 of 24 bits (excluding MSB of first received byte) would give the complete LFSR state. The 8
newly generated LFSR bits after a shift by 8 (last 8 XOR products) will produce the next
expected PRBS byte.
In master/slave configuration of the monitor (STS-48c/VC-4-16c concatenated payloads) more
bytes are needed to recover the LFSR state, because the slaves needs a few bytes to be
synchronized with the J1 byte indicator.
The implemented algorithm requires four PRBS bytes of the same payload to ascertain the LFSR
state. From this recovered LFSR state the next expected PRBS byte is calculated.
An Out of Synchronization and Synchronized State is defined for the monitor. While in progress
of synchronizing to the incoming PRBS stream, the monitor is out of synchronization and
remains in this state until the LFSR state is recovered and the state has been verified by receiving
4 consecutive PRBS bytes without error. The monitor will then change to the Synchronized State
and remains in that state until forced to resynchronize via the RESYNC register bit or upon
receiving 3 bytes with errors. When forced to resynchronize, the monitor changes to the Out of
Synchronization State and tries to regain synchronization.
It is important to note that the monitor can falsely synchronize to an all zero pattern or, if the
incoming pattern is inverted, an all ones pattern. It is recommended that users poll the PRGM
Monitor’s LFSR value after synchronization has been declared to confirm that the value is neither
all 1’s or all 0’s.
23
+X
18
+1 polynomial) or incrementing pattern can be
S/UNI-2488 Telecom Standard Product Datasheet
Released
536