PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 541

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.20 Using the Performance Monitoring Features
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
3. Write the channel number (indirect address) to the indirect address register with RWB set to
4. Read BUSY. Once it equals 0, the indirect write has been completed.
The following steps should be followed for reading indirect registers:
1. Read the BUSY bit. If it is equal to logic 0, continue to step 2. Otherwise, continue polling
2. Write the channel number (indirect address) to the indirect address register with RWB set to
3. Read the BUSY bit. If it is equal to logic 0, continue to 4. Otherwise, continue polling the
4. Read the indirect data register(s) to find the state of the register bits for the selected channel
Note that the TXSDQ and RXSDQ are handled a little bit differently than most TSB’s with
indirect registers. It has several Indirect Data Registers – though only one Indirect Address
register that controls them all. See the TXSDQ and RXSDQ register description for more
information.
The SARC’s indirect registers are also programmed in a slightly different manner. See Section
13.17.1.
A particular idiosyncracy should be noted for the SVCA’s indirect registers. When configured for
concatenated payloads, the value written to SVCA indirect register 2 (diagnostics reg) of a master
timeslot gets propagated to (overwrites) the indirect register 2 values of all slave timeslots
associated to the master timeslot (within the SVCA where the indirect write was performed).
Similarly, when the payload is changed to a higher concat level (eg 12xSTS-1 to STS-12c), the
value previously present in the master timeslot is propagated to (overwrites) the values in the
slave timeslots without any indirect write actions being performed.
When the payload is changed back to a lower concatenation level, the new SVCA indirect register
2 values remain and the old ones are lost.
The same behaviour is observed when writing to indirect register 2 of timeslot 1 (the de-facto
master) of an SVCA configured as a STS-12 slave of an STS-48c payload.
The performance monitor counters within the different blocks are provided for performance
monitoring purposes. The TCFP, RCFP, R8TD, RXSDQ, TXSDQ, RHPP, RRMP, and PRGM all
contain performance monitor registers. The counters have been sized to not saturate if polled
every second.
logic 0.
the BUSY bit.
logic 1.
BUSY bit.
number.
S/UNI-2488 Telecom Standard Product Datasheet
Released
541