PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 542

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.21 Loopback Operation
13.23 JTAG Support
13.22 Required Reset Sequence
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Each block’s counters can be accumulated independently if one of the registers which contain the
latched counter values is written to. A device update of all the counters can be done by writing to
the S/UNI-2488 Global Performance Monitor Update register (register 0000H). After this
register is written to, the TIP bit in this register can be polled to determine when all the counter
values have been transferred and are ready to be read.
There are 3 loopback modes available in the S/UNI-2488. They are shown in Figure 5.
Parallel diagnostic Loopback enables a digital loopback from the transmit line to the receive line
before the 2.488Gbps analog circuitry. It is enabled by setting the PDLE bit in register 0x0001.
Serial Diagnostic Loopback enables a loopback from the transmit 2.488Gbps serial line to the
receive 2.488Gbps serial line. It is enabled by setting the SDLE bit in register 0x0012.
Line Loopback enables a loopback from the receive 2.488Gbps serial line to the transmit
2.488Gbps serial line. It is enabled by setting LINE_LOOP_BACK bit in register 0x0013 and the
SLLE register bit in register 0x0020 to logic 1. The CSU_MODE[7] bit in register 0x0021 must
be set to logic 0.
After digital reset, and before starting any software routines to capture performance monitor
count values, a write to register 0x0000 should be executed to initiate a global performance
monitor count update. Then, the TIP bit in register 0x0000 should be monitored after 32
REFCLK clock periods (approx 102.8ns). If it is logic 1, a software reset (done by setting and
then clearing DRESET in register 0x0001) should be done to clear a TIP lock-up condition.
Repeat this sequence until TIP is read to be logic 0.
If this reset routine is not followed, there is a minute chance that the RHPP’s, the TXSDQ’s, or
the RXSDQ’s performance monitor counters, and the TIP register bit will start up in a lock-up
condition and not operate properly.
The S/UNI-2488 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1
standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS,
TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB
input is the active-low reset signal used to reset the TAP controller. TRSTB should be tied to
RSTB if the JTAG interface is not used. TCK is the test clock used to sample data on input, TDI
and to output data on output, TDO. The TMS input is used to direct the TAP controller through
its states. The basic boundary scan architecture is shown below.
S/UNI-2488 Telecom Standard Product Datasheet
Released
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