PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 543

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
TRSTB
TMS
TCK
TDI
Figure 31 Boundary Scan Architecture
The boundary scan architecture consists of a TAP controller, an instruction register with
instruction decode, a bypass register, a device identification register and a boundary scan register.
The TAP controller interprets the TMS input and generates control signals to load the instruction
and data registers. The instruction register with instruction decode block is used to select the test
to be executed and/or the register to be accessed. The bypass register offers a single-bit delay
from primary input, TDI to primary output, TDO. The device identification register contains the
device identification code.
The boundary scan register allows testing of board inter-connectivity. The boundary scan register
consists of a shift register place in series with device inputs and outputs. Using the boundary scan
register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition,
patterns can be shifted in on primary input, TDI and forced onto all digital outputs.
Controller
Access
Test
Port
Device Identification
Control
Tri-state Enable
Select
Boundary Scan
Instruction
Register
Register
Register
Register
Decode
Bypass
and
S/UNI-2488 Telecom Standard Product Datasheet
Mux
DFF
Released
TDO
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