PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 555

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

14.4
14.4.1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
RDAT[31:0]
RPRTY
RFCLK
RSOC
RENB
RCA
Packet over SONET (POS-PHY) Level 3 System Interface
The Packet over SONET (POS-PHY) Level 3 System Interface is compatible with the OIF-SPI3
specification. The S/UNI-2488 only supports the 32-bit mode of operation.
Transmit PL3 Interface
The Transmit POS-PHY Level 3 System Interface Timing diagram (Figure 41) illustrates the
operation of the system side transmit FIFO interface. TENB is asserted in cycle 2 to start the
transfer. DTPA shows that there is room in the FIFO (the FIFO fill threshold is user
programmable) for PHY address 0. The packet data is transferred on TDAT[31:0] starting at the
rising TFCLK edge at the start of cycle 3. TSOP is also asserted at this cycle to indicate the data
on TDAT[31:24] contains the start-of-packet byte. TENB is deasserted in cycle 3 by the
upstream device to pause the transfer. Data transfer continues in cycle 4. In cycle 6, DTPA is
deasserted indicating that the FIFO for PHY address 0 has fallen below the data available
threshold (TXSDQ’s BT[4:0] register bits). In the example shown here, the upstream device
responds by stopping its transfer immediately at cycle 8 by deasserting TENB. With many set-up
configurations, the upstream device does not need to stop immediately. It can complete the
transfer of one more burst before stopping. See Section 13.12 for details on the behaviour of
DTPA.
Because DTPA is asserted again on cycle 8, transfers can be conducted again. TENB is asserted
again before cycle 11 to continue the transfer. In cycle 11, TEOP is asserted to indicate that
TDAT[31:0] contains one byte which is the end of the packet. TMOD[1:0] is valid at the same
time to indicate which bytes in TDAT[31:0] contain valid data and thus the last byte of the packet
can be inferred. TERR is also valid during this cycle to indicate whether or not this packet should
be aborted because of an upstream error. If TERR is logic 1, the packet will be aborted by the
S/UNI-2488’s packet processor. In cycle 12, TENB is deasserted again.
Figure 40 Receive UTOPIA Level 3 System Interface Timing for Single PHY
1
2
3
4
H1
5
P1
6
S/UNI-2488 Telecom Standard Product Datasheet
7
P10
8
P11
9
P12
10
11
H1
Released
12
P1
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