PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 556

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

14.4.2
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
TDAT[31:0]
TMOD[1:0]
TPRTY
TFCLK
TENB
TSOP
TEOP
TERR
DTPA
TSOP must be high during transfers which contain the first byte of a packet. TEOP must be high
during transfers which contain the last byte of a packet. It is legal to assert TSOP and TEOP at
the same time. This case occurs when TDAT[31:0] contain both the SOP and EOP. When TSOP
is asserted and the previous transfer was not marked with TEOP, the system interface realigns
itself to the new timing, and both the previous packet and the current packet may be corrupted
and aborted.
Figure 41 Transmit POS-PHY Level 3 System Interface Timing
Receive PL3 Interface
The Receive POS-PHY Level 3 System Interface Timing diagram (Figure 42) illustrates the
operation of the system side receive interface. The SUNI-2488 performs the polling operation
internally and pushes data to the downstream reader when it is available.
When data is available, the RVAL signal is asserted. RSX is also asserted in cycle 2 to indicate
that the PHY address (always equal to 0x00 for the S/UNI-2488) for which data is being
transferred is present on RDAT[7:0]. RDAT[31:24] holds the Data Type Field (see register
786H). At cycle 3, RSOP is asserted to indicate that the RDAT[31:24] contains the first byte of a
packet. RENB is deasserted in cycle 4 because the downstream device wants to pause the data
transfer.
Data transfer continues until cycle 10 when RVAL is deasserted. At cycle 12 and 13, the last two
transfers for the packet are performed. In cycle 13, REOP signals the last byte of the packet is
contained in RDAT[31:0] and the value of RMOD[1:0] indicates which bytes in RDAT[31:0]
contain valid data. RERR is asserted along with REOP if errors were detected in this packet
(aborted, length violation, FIFO overrun, FCS errors) so the downstream device may discard the
packet. In cycle 16, the setup for a new transfer is initiated by reasserting RSX and the PHY
address and data type on RDAT[7:0] and RDAT[31:24] respectively. In cycle 17 the new transfer
begins.
The burst length of any transfer can be limited by setting the RXPHY’s BURST_SIZE[7:0]
register bits.
1
2
B1-B4
3
B5-B8
4
5
B41-B44
B45-B48
6
B49-B52
S/UNI-2488 Telecom Standard Product Datasheet
7
8
9
B53-B56
10
11
B57
12
Released
13
B1-B4
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