PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 557

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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14.5
14.5.1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
RDAT[31:0]
RMOD[1:0]
RPRTY
RFCLK
RSOP
REOP
RERR
RENB
RVAL
RSX
ROHCLK
ROHFP
RTOH
The FIFO threshold at which data transfer begins is set by the RXSDQ’s DT[7:0] register bits.
ATM cells can be transferred through the PL3 interface as fixed length packets. The DT[7:0]
value should be set so that only complete ATM cells are transferred.
Figure 42 Receive POS-PHY Level 3 System Interface Timing
Overhead Extraction and Insertion
Transport Overhead Extraction
Figure 43 shows the receive transport overhead (RTOH) functional timings. Transport overhead
insertion is available for STS-1 #1 to 12. ROHCLK is a 20.736 MHz clock generated by gapping
a 25.92 MHz clock (33% high duty cycle). 2592 bits (9x3x12 bytes) are output on RTOH
between two ROHFP assertions.
Figure 43 RTOH Output Timing
Figure 44 shows that RTOH and ROHFP are aligned with the falling edge of ROHCLK. The
rising edge of ROHCLK should be used to sample RTOH and ROHFP. Sampling ROHFP high
identifies the MSB of the first A1 byte on RTOH.
1
2
1000
8
B1-B4
3
A1 #1
A1 #1
B5-B8
4
8
5
B9-B12
A1 #...
A1 #...
6
8
7
A1 #12
A1 #12
B41-B44
8
8
B45-B48
9
A2 #1
A2 #1
S/UNI-2488 Telecom Standard Product Datasheet
10
8
11
A2 #...
A2 #...
B52-B55
12
8
B56-B57
13
A2 #12
A2 #12
14
8
15
16
1000
J0
J0
Released
17
8
557

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