PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 6

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Issue
No.
Issue
Date
Details of Change
Added minimum RSTB pulse width in AC timing section.
G1[7:0] register bits in THPP Transmit G1 POH and H4 Mask register
now reference SRCG1 register bit as the enabling bit rather than
SRCREI and SRCRDI bits.
Changed recommended external CRU capacitor value to 10nF and
external CSU capacitor value to 100nF.
Updated internal resistance values and descriptions for CRU2488 and
CSU2488 that are selected via CRU_MODE and CSU_MODE register
bits.
Removed CRU DC-offset and self narrowbanding modes.
Modified FSBEN register bit in THPP Control Register (indirect register
0) to identify which timeslots are valid.
Removed CSU_CLOCK register bit in register 0x0010. It is unused
since the JAT CSU is to be permanently reset and bypassed.
Corrected CRU_CLOCK description in register 0x010 to reference
register 0x010 instead of 0x00.
TXPHY’s INBANDADDR register bit renamed to Reserved0 and added
comment that its default value of logic 1 must be cleared to logic 0 for
proper operation.
Added Z0DEF register bit must be set to logic 0.
Added Section 13.17 to describe using the SARC.
Added jitter requirement for APSIFPCLK.
Highlighted need to assert SARC’s PAISPTREN to enable AIS-P
consequential actions.
Updated analog power supply filtering.
Added typical jitter numbers in RCLK and TCLK pin descriptions.
Added comments about CSU and CRU lock-up conditions.
Added comment to set bit 0 of register 0038H to logic 1.
Removed registers 0x20E and 0x2F from register map.
Removed TSLDEL register bit.
Removed statement about DCC input pins.
Modified microprocessor AC timing diagrams to include WCIMODE = 1
feature.
Modified statement regarding control circuitry for SONET wander
transfer, holdover, and stability.
Included reset start-up procedure to overcome the potential pmon
counter lock-up condition in the RHPPs and SDQs.
Enhanced desription for K.28.0 character of serial TeleCombus
mapping in Sections 13.1.10 and 13.1.11.
Added statement in Section 13.2 that states that consequential action
of asserting RDI-P is not supported.
Updated B3E signal description to state that it is only valid for OC48c
S/UNI-2488 Telecom Standard Product Datasheet
Released
6