PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 62

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Pin Name
RSX
TFCLK
TDAT[31]
TDAT[30]
TDAT[29]
TDAT[28]
TDAT[27]
TDAT[26]
TDAT[25]
TDAT[24]
TDAT[23]
TDAT[22]
TDAT[21]
TDAT[20]
TDAT[19]
TDAT[18]
TDAT[17]
TDAT[16]
TDAT[15]
TDAT[14]
TDAT[13]
TDAT[12]
TDAT[11]
TDAT[10]
TDAT[9]
TDAT[8]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
Type
Output
Input
Input
Pin
No.
R29
B18
B5
D7
A5
B6
C7
D8
A6
B7
D9
A7
B8
C9
A8
B9
C10
D11
B10
C11
D12
A10
C12
A11
D13
B12
C13
A12
B13
D14
C14
B14
A14
C15
Function
The POS-PHY receive start of transfer (RSX) signal
indicates the start of a packet transfer. When RSX is high,
the channel number being transferred is given on RDAT[31:0].
RSX is only used for POS-PHY operation and is updated on
the rising edge of RFCLK.
The UTOPIA transmit FIFO write clock (TFCLK) signal is
used to write ATM cells to the transmit FIFO.
TFCLK is expected to cycle at a 104 MHz rate.
The POS-PHY transmit FIFO write clock (TFCLK) signal is
used to write packet data into the transmit packet FIFO.
TFCLK is expected to cycle at a 104 MHz rate.
The UTOPIA transmit cell data (TDAT[31:0]) bus carries the
ATM cell octets that are written to the transmit FIFO.
TDAT[31:0] is considered valid only when TENB is
simultaneously asserted.
TDAT[31:0] is sampled on the rising edge of TFCLK.
The POS-PHY transmit packet data (TDAT[31:0]) bus
carries the POS packet octets that are written to the transmit
FIFO.
The TDAT[31:0] bus is considered valid only when TENB is
simultaneously asserted.
TDAT[31:0] is sampled on the rising edge of TFCLK.
S/UNI-2488 Telecom Standard Product Datasheet
Released
62

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