PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 85

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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10.5.3
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
LOPC is declared on entry to the LOPC_state after eight consecutive pointers with values other
than concatenation indications
PAISC is declared on entry to the AISC_state after three consecutive AIS indications
Error Monitoring
The RHPP calculates the path BIP-8 error detection codes on the SONET (SDH) payloads. The
path BIP-8 code is based on a bit interleaved parity calculation using even parity. The calculated
BIP-8 codes are compared with the BIP-8 codes extracted from the B3 byte of the STS (VC)
payload of the following frame. Any differences indicate a path BIP-8 error. The RHPP
accumulates path BIP-8 errors in a microprocessor readable 16 bits saturating counter (up to 1
second accumulation time). Optionally, block BIP-8 errors can be accumulated.
The RHPP extracts the path remote error indication (REI-P) errors from bits 1, 2, 3 and 4 of the
path status byte (G1) and accumulates them in a microprocessor readable 16 bits saturating
counter (up to 1 second accumulation time). Optionally, block REI errors can be accumulated.
The RHPP monitors the path signal label byte (C2) payload to validate change in the accepted
path signal label (APSL). The same PSL byte must be received for three or five consecutive
frames (selectable by the PSL5 bit in the configuration register) before being considered
accepted.
The RHPP also monitors the path signal label byte (C2) to detect path payload label unstable
(PLU-P) defect. A PSL unstable counter is increment every time the received PSL differs from
the previously accepted PSL (an erroneous PSL will cause the counter to be increment twice,
once when the erroneous PSL is received and once when the error free PSL is received). The PSL
unstable counter is reset when the same PSL value is received for three or five consecutive frames
(selectable by the PSL5 bit in the configuration register). PLU-P is declared when the PSL
unstable counter reaches five. PLU-P is removed when the PSL unstable counter is reset.
The RHPP also monitors the path signal label byte (C2) to detect path payload label mismatch
(PLM-P) defect. PLM-P is declared when the accepted PSL does not match the expected PSL
according to Table 1. PLM-P is removed when the accepted PSL match the expected PSL
according to Table 1. The accepted PSL is the same PSL value received for three or five
consecutive frames (selectable by the PSL5 bit in the configuration register). The expected PSL
is a programmable PSL value.
The RHPP also monitors the path signal label byte (C2) to detect path unequipped (UNEQ-P)
defect. UNEQ-P is declared when the accepted PSL is 00H and the expected PSL is not 00H.
UNEQ-P is removed when the accepted PSL is not 00H or when the accepted PSL is 00H and the
expected PSL is 00H. The accepted PSL is the same PSL value received for three or five
consecutive frames (selectable by the PSL5 bit in the configuration register). The expected PSL
is a register programmable PSL value.
S/UNI-2488 Telecom Standard Product Datasheet
Released
85

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