PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 94

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

10.7.10 POS Performance Monitor
10.8
10.8.1
10.8.2
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
The Performance Monitor consists of four 16-bit saturating error event counters, one 32-bit
saturating received good packet counter, and one 40-bit counter for accumulating packet bytes.
One of the error event counters accumulates FCS errors. The second error event counter
accumulates minimum length violation packets. The third error event counter accumulates
maximum length violation packets. The fourth error event counter accumulates aborted packets.
The 32-bit receive good packet counter counts all error free packets.
Each counter may be read through the microprocessor interface. Circuitry is provided to latch
these counters so that their values can be read while simultaneously resetting the internal counters
to 0 or 1, whichever is appropriate, so that a new period of accumulation can begin without loss
of any events. The counters should be polled at least once per second so error events will not be
missed.
The RCFP monitors the packets for both minimum and maximum length errors. When a packet
size is smaller than MINPL[7:0], the packet is marked with an error but still written into the
FIFO. Malformed packets, that is packets that do not at least contain four bytes, are discarded
and will be counted as a minimum packet size violation. When the packet size exceeds
MAXPL[16:0], the packet is marked with an error and the bytes beyond the maximum count are
discarded.
Receive Scalable Data Queue (RXSDQ)
The RXSDQ provides a FIFO to separate the line-side timing from the higher layer ATM/POS
link layer timing. The RXSDQ has two modes of operations, ATM and POS.
Receive ATM FIFO
The RXSDQ is responsible for holding up to 48 cells until they are read by the Receive System
Interface.
Receive FIFO management functions include filling the receive FIFO, indicating when cells are
available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers,
and detecting FIFO overrun conditions. Upon detection of an overrun, the FIFO discards the
current cell and discards the incoming cells until there is room in the FIFO. FIFO overruns are
indicated through a maskable interrupt and register bit and are considered a system error.
Receive POS FIFO
The RXSDQ contains 192 sixteen-byte blocks for FIFO storage, along with management circuitry
for reading and writing the FIFO. Note that packets always begin at the beginning of a block and
will not use up left-over space in a block used by a previous packet. The receive FIFO provides
for the separation of the physical layer timing from the system timing.
S/UNI-2488 Telecom Standard Product Datasheet
Released
94