PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 95

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

10.9
10.9.1
10.9.2
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Receive FIFO management functions include filling the receive FIFO, indicating when packets or
bytes are available to be read from the receive FIFO, maintaining the receive FIFO read and write
pointers, and detecting FIFO overrun and underrun conditions. Upon detection of an overrun, the
FIFO aborts the current packet and discards the current incoming bytes until there is room in the
FIFO. Once enough room is available, as defined by the BT[7:0] register bit settings, the RXSDQ
will wait for the next start of packet before writing any data into the FIFO. FIFO overruns are
indicated through a maskable interrupt and register bit and are considered a system error. A FIFO
underrun is caused when the System Interface tries to read more data words while the FIFO is
empty. This action will be detected and reported through the FUDRI interrupt, but it is not
considered a system error. The system will continue to operate normally. In that situation, RVAL
can be used by the Link Layer device to find out if valid or invalid data is provided on the System
Interface.
Receive Phy Interface (RXPHY)
The S/UNI-2488 receive system interface can be configured for ATM or POS mode. When
configured for ATM applications, the system interface provides a 32-bit Receive UTOPIA Level 3
compatible bus to allow the transfer of ATM cells between the ATM layer device and the S/UNI-
2488. When configured for POS applications, the system interface provides either a 32-bit POS-
PHY Level 3 compliant bus for the transfer of ATM cells and data packets between the link layer
device and the S/UNI-2488. The link layer device can implement various protocols, including
PPP and HDLC.
Receive UTOPIA Level 3 Interface
The UTOPIA Level 3 compliant interface accepts a read clock (RFCLK) and read enable signal
(RENB). The interface indicates the start of a cell (RSOC) when data is read from the receive
FIFO (using the rising edges of RFCLK). The RCA signal indicates when a cell is available for
transfer on the receive data bus RDAT[31:0]. The RPRTY signal reports the parity on the
RDAT[31:0] bus (selectable as odd or even parity). This interface also indicates FIFO overruns
via a maskable interrupt and register bits. Read accesses while RCA is deasserted will output
invalid data.
Receive POS-PHY Level 3
The interface accepts a read clock (RFCLK) and read enable signal (RENB) when data is read
from the receive FIFO (using the rising edge of the RFCLK). The start of packet RSOP marks
the first byte of receive packet data on the RDAT[31:0]. The RPRTY signal determine the parity
on the RDAT[31:0] bus (selectable as odd or even parity). The end of a packet is indicated by the
REOP signal. Signal RERR is provided to indicate that an error in the received packet has
occurred (the error may have several causes include an abort sequence or an FCS error). The
RVAL signal is used to indicate when RSOP, REOP, RERR and RDAT[31:0] are valid. Read
accesses while RVAL is logic 0 are ignored and will output invalid data. RSX indicates the start
of a transfer and marks the clock cycle where the in-band channel address is given on the RDAT
bus. The RXPHY performs the polling procedure to select which PHY address is serviced.
S/UNI-2488 Telecom Standard Product Datasheet
Released
95