PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet
PM4328-PI
Available stocks
Related parts for PM4328-PI
PM4328-PI Summary of contents
Page 1
... STANDARD PRODUCT DATASHEET PMC-2011596 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 1 PM4328 TECT3 DATASHEET ISSUE 1: AUGUST 2001 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 2
... PERFORMANCE MONITOR COUNTERS (T1/E1-PMON) .........62 9.4 BIT ORIENTED CODE DETECTOR (RBOC) ..............................63 9.5 HDLC RECEIVER (RDLC)...........................................................63 9.6 T1 ALARM INTEGRATOR (ALMI)................................................64 9.7 ELASTIC STORE (ELST) ............................................................65 9.8 SIGNALING ELASTIC STORES (RX-SIG-ELST AND TX_SIG- ELST)...........................................................................................65 9.9 SIGNALING EXTRACTOR (SIGX)...............................................66 PROPRIETARY AND CONFIDENTIAL ISSUE 1 i PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 3
... PERFORMANCE MONITOR ACCUMULATOR (DS3-PMON) .....80 9.24 DS3 TRANSMITTER (DS3-TRAN) ..............................................81 9.25 M23 MULTIPLEXER (MX23)........................................................82 9.26 DS2 FRAMER (DS2-FRMR) ........................................................82 9.27 M12 MULTIPLEXER (MX12)........................................................84 9.28 EGRESS SYSTEM INTERFACE (ESIF) ......................................85 9.29 INGRESS SYSTEM INTERFACE (ISIF) ......................................91 9.30 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT (EXSBI) .....................................................................................................96 PROPRIETARY AND CONFIDENTIAL ISSUE 1 ii PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 4
... DS3 LOOPBACK MODES .........................................................154 12.10 SBI BUS DATA FORMATS.........................................................157 12.11 H-MVIP DATA FORMAT.............................................................166 12.12 SERIAL CLOCK AND DATA FORMAT .......................................170 12.13 PRGD PATTERN GENERATION ...............................................170 12.14 JTAG SUPPORT........................................................................175 13 FUNCTIONAL TIMING .........................................................................183 PROPRIETARY AND CONFIDENTIAL ISSUE 1 iii PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 5
... FIGURE 2: HIGH DENSITY FRAME RELAY APPLICATION ............................15 FIGURE 3: TECT3 BLOCK DIAGRAM..............................................................17 FIGURE 4: M13 MULTIPLEXER BLOCK DIAGRAM ........................................18 FIGURE 5: DS3 FRAMER ONLY MODE BLOCK DIAGRAM ............................19 FIGURE 6: PIN DIAGRAM ................................................................................25 FIGURE 7: CRC MULTIFRAME ALIGNMENT ALGORITHM ............................59 PROPRIETARY AND CONFIDENTIAL ISSUE 1 iv PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 6
... FIGURE 25: CLOCK SLAVE: H-MVIP...............................................................94 FIGURE 26: CLOCK SLAVE: SERIAL DATA AND H-MVIP CCS ......................95 FIGURE 27: DS3 FRAME STRUCTURE ........................................................134 FIGURE 28: FER COUNT VS. BER (E1 MODE) ............................................138 FIGURE 29: CRCE COUNT VS. BER (E1 MODE)..........................................139 PROPRIETARY AND CONFIDENTIAL ISSUE 1 v PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 7
... FIGURE 48: RECEIVE BIPOLAR DS3 STREAM............................................183 FIGURE 49: RECEIVE UNIPOLAR DS3 STREAM .........................................183 FIGURE 50: TRANSMIT BIPOLAR DS3 STREAM .........................................184 FIGURE 51: TRANSMIT UNIPOLAR DS3 STREAM.......................................184 FIGURE 52: FRAMER MODE DS3 TRANSMIT INPUT STREAM ..................185 PROPRIETARY AND CONFIDENTIAL ISSUE 1 vi PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 8
... FIGURE 67: E1 EGRESS INTERFACE CLOCK SLAVE : EXTERNAL SIGNALING MODE......................................................................192 FIGURE 68: T1 EGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EFP ENABLED MODE ........................................................................193 FIGURE 69: T1 EGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EXTERNAL SIGNALING MODE......................................................................194 PROPRIETARY AND CONFIDENTIAL ISSUE 1 vii PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 9
... FIGURE 86: SBI DROP BUS COLLISION AVOIDANCE TIMING ...................216 FIGURE 87: H-MVIP EGRESS DATA & FRAME PULSE TIMING...................218 FIGURE 88: H-MVIP INGRESS DATA TIMING ...............................................219 FIGURE 89: XCLK INPUT TIMING .................................................................220 PROPRIETARY AND CONFIDENTIAL ISSUE 1 viii PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 10
... TABLE 2: REGISTER MEMORY MAP ..............................................................99 TABLE 3: INSTRUCTION REGISTER ............................................................121 TABLE 4: IDENTIFICATION REGISTER.........................................................122 TABLE 5: BOUNDARY SCAN CHAIN .............................................................122 TABLE 6: PMON COUNTER SATURATION LIMITS (E1 MODE) ...................137 TABLE 7: PMON COUNTER SATURATION LIMITS (T1 MODE) ...................137 PROPRIETARY AND CONFIDENTIAL ISSUE 1 ix PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 11
... TABLE 25: CCS E1 H-MVIP FORMAT IN G.747 MODE .................................168 TABLE 26: PSEUDO RANDOM PATTERN GENERATION (PS BIT = 0)........173 TABLE 27: REPETITIVE PATTERN GENERATION (PS BIT = 1)...................174 TABLE 28: ABSOLUTE MAXIMUM RATINGS ................................................199 TABLE 29: D.C. CHARACTERISTICS ............................................................200 TABLE 30: MICROPROCESSOR INTERFACE READ ACCESS ....................202 PROPRIETARY AND CONFIDENTIAL ISSUE 1 x PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 12
... TABLE 46: INGRESS INTERFACE TIMING - CLOCK SLAVE MODES (FIGURE 96)................................................................................................227 TABLE 47: INGRESS INTERFACE TIMING - CLOCK MASTER MODES (FIGURE 97)................................................................................229 TABLE 48: TRANSMIT LINE INTERFACE TIMING (FIGURE 98)...................230 TABLE 49: JTAG PORT INTERFACE .............................................................232 PROPRIETARY AND CONFIDENTIAL ISSUE 1 xi PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 13
... STANDARD PRODUCT DATASHEET PMC-2011596 TABLE 50: ORDERING AND THERMAL INFORMATION ...............................234 TABLE 51: THERMAL INFORMATION – THETA JA VS. AIRFLOW ...............234 PROPRIETARY AND CONFIDENTIAL ISSUE 1 xii PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 14
... Provides per-DS0 line loopback and per link diagnostic and line loopbacks. · Provides an on-board programmable binary sequence generator and detector for error testing at DS3 rates. Includes support for patterns recommended in ITU-T O.151. PROPRIETARY AND CONFIDENTIAL ISSUE 1 1 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 15
... Frames to DS-1 signals in SF and ESF formats. · Frames to TTC JT-G.704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation for Japanese applications. · Accepts gapped data streams to support higher rate demultiplexing. PROPRIETARY AND CONFIDENTIAL ISSUE operation. 2 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 16
... Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications. · Provides an HDLC interface with 128 bytes of buffering for terminating the national use bit data link. PROPRIETARY AND CONFIDENTIAL ISSUE 1 3 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER –1, 2 – ...
Page 17
... N*8kHz reference. · Provides minimum ones density through Bell (bit 7), GTE or “jammed bit 8” zero code suppression on a per-DS0 basis. PROPRIETARY AND CONFIDENTIAL ISSUE 1 4 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER –1, 2 – ...
Page 18
... Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. · Provides a digital phase locked loop for generation of a low jitter transmit clock. PROPRIETARY AND CONFIDENTIAL ISSUE 1 5 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER –1, 2 – ...
Page 19
... C-bit parity mode operation 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second. PROPRIETARY AND CONFIDENTIAL ISSUE 1 6 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER –1, 2 – ...
Page 20
... Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled and interrupt-driven operation. · Provides programmable pseudo-random test sequence generation ( bit length sequences conforming to ITU-T O.151 standards) or any PROPRIETARY AND CONFIDENTIAL ISSUE 1 7 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 21
... Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end receive failure (FERF). · Accumulates up to 255 DS2 M-bit or F-bit error events per second. PROPRIETARY AND CONFIDENTIAL ISSUE 1 8 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 22
... In normal mode, E1 timeslots are bundled from 4 E1 links in sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20 and 21 by itself). In G.747 mode, E1 timeslots are bundled from 3 E1 links in sequential order, spaced by a reserved timeslot on every 4th frame (i.e. 1-3/X, 4-6/X, 7-9/X, 10-12/X, 13-15/X, 16-18/X, 19-21/X). PROPRIETARY AND CONFIDENTIAL ISSUE 1 9 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 23
... Transmit timing is mastered either by the TECT3 or a layer 2 device connecting to the SBI bus. Timing mastership is selectable on a per tributary basis, where a tributary is either an individual DS3. PROPRIETARY AND CONFIDENTIAL ISSUE 1 10 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 24
... Frame Relay switches and access devices (FRADS) · M23 Based M13 Multiplexer · C-Bit Parity Based M13 Multiplexer · Channelized and Unchannelized DS3 Frame Relay Interfaces PROPRIETARY AND CONFIDENTIAL ISSUE 1 11 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 25
... Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue 5, December, 1993 · Bell Communications Research - OTGR: Network Maintenance Transport Surveillance - Generic Digital Transmission Surveillance, TR-TSY-000820, Section 5.1, Issue 1, June 1990 PROPRIETARY AND CONFIDENTIAL ISSUE 1 12 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 26
... Networks which are Based on the 2048 kbit/s Hierarchy, 03/94 · ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Ex–hange (LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994. PROPRIETARY AND CONFIDENTIAL ISSUE 1 13 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 27
... Nippon Telegraph and Telephone Corporation - Technical Reference for High- Speed Digital Leased Circuit Services, Third Edition, 1990. · GO-MVIP, Multi-Vendor Integration Protocol, MVIP-90, Release 1.1, 1994 · GO-MVIP, H-MVIP Standard, Release1.1a, 1997 PROPRIETARY AND CONFIDENTIAL ISSUE 1 14 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 28
... T1/21 E1 Framer M13 Mux, DS3 framer PM4328 TECT3 28 T1/21 E1 Framer M13 Mux, DS3 framer PM4328 TECT3 28 T1/21 E1 Framer M13 Mux, DS3 framer 15 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER PM73122 AAL1gator-32 ATM SAR PM73122 AAL1gator-32 ATM SAR PM73122 AAL1gator-32 ATM SAR ...
Page 29
... H-MVIP interfaces. DS3 line side access is via the clock and data interface for line interface units. Unchannelized DS3 system side access is available through a serial clock and data interface or the SBI bus, both shown at the top of the diagram. PROPRIETARY AND CONFIDENTIAL ISSUE 1 16 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 30
... STANDARD PRODUCT DATASHEET PMC-2011596 Figure 3: TECT3 Block Diagram PROPRIETARY AND CONFIDENTIAL ISSUE 1 17 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 31
... A tte nua to r Extraction DEMUX ELST Elastic Store One of Seven FRAM FRMR/M12s Framer RAM One PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER XCLK CTCLK CM V 8MC LK CM VFP B MV ED[1:7] CA SED[1:7] T PSC E SIF Per-D S0 Egress ...
Page 32
... RNEG / RDLC R x HDLC PROPRIETARY AND CONFIDENTIAL ISSUE TRAN DS3 Transm it Fram er FRM R DS3 R eceive Fram Perf. M onitor 19 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER TFP O/TMFPO /TG APC LK TFP I APCLK/RSCLK RD ATO RFPO /R MFPO RO VRHD ...
Page 33
... DATASHEET PMC-2011596 6 DESCRIPTION The PM4328 High Density T1/E1 Framer with Integrated M13 Multiplexer (TECT3 feature-rich device for use in any applications requiring high density link termination over channelized DS3. The TECT3 supports asynchronous multiplexing and demultiplexing of 28 DS1s into a DS3 signal as specified by ANSI T1.107 and Bell Communications Research TR-TSY-000009 ...
Page 34
... Serial PCM interfaces to each T1 framer allow 1.544 Mbit/s ingress/egress system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. PROPRIETARY AND CONFIDENTIAL ISSUE 1 21 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 35
... When enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication PROPRIETARY AND CONFIDENTIAL ISSUE 1 22 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER -3 bit error rate and detects -3 ...
Page 36
... DS2. AIS may be inserted in any of the low speed tributaries in both multiplex and demultiplex directions. When configured as a DS3 framer the unchannelized payload of the DS3 link is available to an external device. PROPRIETARY AND CONFIDENTIAL ISSUE 1 23 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 37
... The TECT3 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface. PROPRIETARY AND CONFIDENTIAL ISSUE 1 24 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 38
... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Bottom View 25 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER VSS VSS VSS VSS VSS VSS ...
Page 39
... RCLK by default and may be enabled to be sampled on the falling edge of RCLK by setting the RFALL bit in the DS3 Master Receive Line Options register. circuitry downstream of the DS3 transmitter of the TECT3. TCLK is nominally a 44.736 MHz, 50% duty cycle clock. 26 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 40
... TICLK is nominally a 44.736 MHz, 50% duty cycle clock. This clock is only required when using the DS3 transmitter with the DS3 line side interface. When not used this clock input should be connected to ground. 27 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 41
... TECT3 is configured as a DS3 framer by setting the OPMODE[1:0] bits in the Global Configuration register. RDATO is the received data aligned to RFPO/RMFPO and ROVRHD. RDATO is updated on either the falling or rising edge of RGAPCLK or RSCLK, depending on the value of 28 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 42
... RSCLK depending on the setting of the RSCLKR bit in the DS3 Master Unchannelized Interface Options register. This signal shares a signal pin with ID[2] and CASID[1]. This signal will be ROVRHD only when enabled for unchannelized DS3 operation. 29 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 43
... DS3 operation this signal will be TFPO/TMFPO/TGAPCLK, otherwise it will be ECLK[1]. AB4 Framer Transmit Data (TDATI). TDATI contains the serial data to be transmitted when the TECT3 is configured as a DS3 framer by setting the 30 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 44
... TICLK or TGAPCLK by setting the TDATIFALL bit to 1in the DS3 Master Unchannelized Interface Options register. This signal shares a signal pin with ED[2] and CASED[1]. This signal will be TFPI/TMFPI only when enabled for unchannelized DS3 operation. 31 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 45
... K22 ICLK[x]. When Clock Master: NxDS0 mode is active, K21 ICLK[x] is gapped during the pulse on IFP[x]. When Y1 the Clock Slave ingress modes are active, IFP[ updated on the active edge of CICLK. I the Clear F4 32 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 46
... H-MVIP CAS signals CASID[1:7]. ID[1] shares D12 a pin with the DS3 system interface signal RDATO. U2 ID[2] shares a pin with the DS3 system interface signal V4 ROVRHD. ID[15,16,19,20,23,24,27,28] shares pins D11 with the SBI interface bus SDDATA[7:0]. A11 M19 L19 D10 A10 33 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 47
... CTCLK, or from CTCLK after jitter attenuation multiple of 8kHz (Nx8khz, where 1£N£256) so long as CTCLK is jitter-free when divided down to 8kHz (in which case the transmit clock is 34 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 48
... T1 mode, on the first F- bit of the multiframe. CEFP is sampled on the active edge of CECLK as selected by the CEFE bit in the Master Common Egress Serial and H-MVIP Interface Configuration register. CEFP has no effect in the Clock Master egress modes. 35 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 49
... H-MVIP CAS signals CASED[1:7]. ED[1] D6 shares a pin with the DS3 system interface signal C7 TDATI. ED[2] shares a pin with the DS3 system P2 interface signal TFPI/TMFPI. M1 ED[7,8,11,12,15,16,19,20,23,24,27,28] shares pins D4 with the SBI interface add bus signals. B6 C20 E22 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 50
... Each channel’s signaling bits are in bit locations 5,6,7,8 of the channel and are frame-aligned by the common egress frame pulse, CEFP. ESIG[x] is sampled on the active edge of CECLK. 37 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 51
... Common H-MVIP Frame Pulse (CMVFPB). The active low common frame pulse for 8.192 Mbps H- MVIP signals references the beginning of each frame for links operating in 8.192Mbps H-MVIP mode. The H-MVIP interfaces are enabled via the 38 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 52
... CMVFPC, and frame pulse, CMVFPB. CASID[x] is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master Common Ingress Serial and H-MVIP Interface 39 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 53
... H-MVIP Interface Configuration register mode only MVED[1:6] are used. MVED[1:7] shares the same pins as ED[1,5,9,13,17,21,25]. AA3 Channel Associated Signaling Egress Data N22 (CASED[1:7]). CASED[x] carries the channel R4 associated signaling stream to be transmitted in the T1 40 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 54
... CMVFPB. CCSED is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. 41 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 55
... positive integer). In synchronous SBI mode, however, SC1FP is used to indicate T1 signaling multiframe alignment, and thus should be asserted for a single SREFCLK cycle once every 12 SBI mutiframes (48 T1 frames or 116640 SREFCLK cycles output, SC1FP is generated on the rising edge 42 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 56
... SBI bus structure. The TECT3 only monitors the add bus payload active signal during the tributary timeslots assigned to this device. SAPL is sampled on the rising edge of SREFCLK. 43 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 57
... octet. The Link Layer device responds to this request by not sending an octet during the octet of the next multi-frame. The TECT3 only drives the justification request signal during the tributary timeslots assigned to this device. SAJUST_REQ is updated on the rising edge of SREFCLK. 44 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 58
... SDPL is updated on the rising edge of SREFCLK. This signal shares a pin with IFP[27]. A9 System Drop Bus Payload Indicator (SDV5). The payload indicator locates the position of the floating payloads for each tributary within the SBI bus 45 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 59
... SBI bus. Each SBI device driving the bus also drives an SBI active signal (SBIACT). This pair of activity detection inputs monitors the active signals from two other SBI devices. When unused this signal should be connected to ground. 46 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 60
... RDB and CSB are low. C15 Active Low Write Strobe (WRB). This signal is low during a TECT3 register write access. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. 47 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 61
... It allows the TECT3 to interface to a multiplexed address/data bus. The ALE input has an integral pull up resistor. C3 Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. 48 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 62
... Note that if not used, TRSTB must be connected to the RSTB input Connect. These pins are not connected to any B2 internal logic. A11 AB11 AB8 W7 W8 AB9 W9 Y10 AA10 AB10 W10 Y11 49 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 63
... Power (VDD2.5[8:1]). The VDD2.5[8:1] pins should R2 be connected to a well-decoupled +2.5V DC power AA8 supply. AA15 R21 H21 A15 C9 Ground (VSS3.3[45:1]). The VSS3.3[45:1] pins Y12 should be connected to GND. L20 B12 AA4 Y9 W11 Y14 Y17 AA19 V21 50 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 64
... W13 AA13 Y13 W14 AB14 W15 W16 AB15 W17 AB16 Y16 AA16 AB17 AB13 AB12 AA17 AB18 W18 AA18 AB19 W19 AA2 Ground (VSSQ[4:1]). The VSSQ[4:1] pins should be Y12 connected to GND. L20 B12 51 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 65
... J12 conductivity. J11 J10 J9 K14 K13 K12 K11 K10 K9 L14 L13 L12 L11 L10 L9 M14 M13 M12 M11 M10 M9 N14 N13 N12 N11 N10 N9 P14 P13 P12 52 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 66
... STANDARD PRODUCT DATASHEET PMC-2011596 Pin Name Type VSS[3] VSS[2] VSS[1] PROPRIETARY AND CONFIDENTIAL ISSUE 1 Pin Function No. P11 P10 P9 53 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 67
... Power to the VDD3.3 and VDDQ pins should be applied before power to the VDD2.5 pins is applied. Similarly, power to the VDD2.5 pins should be removed before power to the VDD3.3 and VDDQ pins are removed. 9. All TECT3 inputs are 5V tolerant. PROPRIETARY AND CONFIDENTIAL ISSUE 1 54 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 68
... PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1-FRMR also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based PROPRIETARY AND CONFIDENTIAL ISSUE 1 55 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 69
... Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe. Basic Frame Alignment Procedure The E1-FRMR searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2. PROPRIETARY AND CONFIDENTIAL ISSUE 1 56 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 70
... The E1-FRMR searches for CRC multiframe alignment by observing whether the International bits (bit NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC PROPRIETARY AND CONFIDENTIAL ISSUE 1 57 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER -3 bit error rate. The -3 ...
Page 71
... PCM data stream, but is unable to achieve CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed non CRC-4 interface. The details of this algorithm are illustrated in the state diagram in Figure 7. PROPRIETARY AND CONFIDENTIAL ISSUE 1 58 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 72
... BFA_Par 8m s expire and NOT( 400 ms exp ire FA_ Par CRCto non-C RC Interworking CR CM FA_ Par (Op tional setting) 59 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER NF AS not found nex t fram not found nex t fram e Start 8ms timer ...
Page 73
... E1-FRMR stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In this mode, the E1-FRMR may be PROPRIETARY AND CONFIDENTIAL ISSUE 1 Out of Frame Yes Yes Yes PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Out of Offline Frame Yes Yes Yes No No ...
Page 74
... CAS multiframe alignment is also declared if basic frame alignment has been lost. National Bit Extraction The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4] , Sa5[1:4] , Sa6[1:4] , Sa7[1:4] and Sa8[1:4]. The PROPRIETARY AND CONFIDENTIAL ISSUE 1 -3 bit error rate. 61 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 75
... When the transfer clock signal is applied, the PMON transfers the counter values into PROPRIETARY AND CONFIDENTIAL ISSUE 1 62 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER -3 mean bit error rate. ...
Page 76
... The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS). PROPRIETARY AND CONFIDENTIAL ISSUE 1 Th code (111111) is similar to the 63 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 77
... Alarm indication is provided through internal register bits. PROPRIETARY AND CONFIDENTIAL ISSUE 1 64 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER -3 bit error rate. ...
Page 78
... There are two additional elastic stores used to adapt the differences in rate between the CAS or CCS H-MVIP signaling rates and the serial clock and data or SBI data rates when in simultaneous SBI or serial clock and data with PROPRIETARY AND CONFIDENTIAL ISSUE 1 65 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 79
... The SIGX block provides one superframe or signaling-multiframe of signal freezing on the occurrence of slips. When a slip event occurs, the SIGX freezes PROPRIETARY AND CONFIDENTIAL ISSUE 1 66 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 80
... Transmit Framing and Bypass Options register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from the egress stream can be by-passed to the output data stream via the same T1/E1 Transmit PROPRIETARY AND CONFIDENTIAL ISSUE 1 67 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 81
... When enabled, the Signaling Aligner is positioned in the egress path before the T1-XBAS. Its purpose is to ensure that if the signaling on ESIG[x] is changed in the middle of a superframe, the XBAS completes transmitting the A,B,C, and D PROPRIETARY AND CONFIDENTIAL ISSUE 1 68 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 82
... The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a PROPRIETARY AND CONFIDENTIAL ISSUE 1 69 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 83
... The performance report takes precedence over incompletely written packets, but it does not pre-empt packets already being transmitted. See the Operation section for details on the performance report encoding. PROPRIETARY AND CONFIDENTIAL ISSUE 1 70 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 84
... The divisors are set using the TJAT and RJAT Jitter Attenuator Divider N1 and N2 registers. The following formula must be met in order to select the values of N1 and N2: Fin/( Fout/( PROPRIETARY AND CONFIDENTIAL ISSUE 1 71 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 85
... II customer interface given in ANSI T1.403 to be met. The DJAT meets the E1 jitter attenuation requirements of the ITU-T Recommendations G.737, G.738, G.739 and G.742. PROPRIETARY AND CONFIDENTIAL ISSUE 1 72 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 86
... XCLK divided by 24 and that of the input data clock. Figure 8: DJAT Jitter Tolerance T1 Modes 100 28 10 Jitter Amplitude, UIpp 1.0 0.1 0.01 1 PROPRIETARY AND CONFIDENTIAL ISSUE 1 10 4.9 100 0.3k Jitter Frequency PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER DJAT minimum tolerance acceptable unacceptable 1k 10k 100k 29 0.2 ...
Page 87
... An XCLK input accuracy of ±100 ppm is only acceptable if an accurate line rate reference is provided. If TJAT is left to free-run without a reference, or referenced to a derivative of XCLK, then XCLK accuracy must be ±32 ppm. PROPRIETARY AND CONFIDENTIAL ISSUE 1 74 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 88
... Hz are attenuated at a level per octave, as shown in Figure 12. PROPRIETARY AND CONFIDENTIAL ISSUE 100 200 250 0 32 XCLK Accuracy 200 300 308 49 100 75 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 300 354 Hz 100 ± ppm 42.4 39 34.9 Hz ± ppm ...
Page 89
... Hz are attenuated at a level per octave, as shown in Figure 13. Figure 13: DJAT Jitter Transfer E1 Modes PROPRIETARY AND CONFIDENTIAL ISSUE 1 62411 62411 min max DJAT response 10 100 6.6 Jitter Frequency PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 43802 max 1k 10k ...
Page 90
... DS3 payload. Patterns may be generated in the transmit direction, and detected in the receive direction. Two types of ITU-T O.151 compliant test patterns are provided : pseudo-random and repetitive. PROPRIETARY AND CONFIDENTIAL ISSUE 1 77 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER -1, 2 ...
Page 91
... DS3 stream are examined. An out-of-frame defect is detected when 3 F-bit errors out consecutive F-bits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration Register), or when one or more PROPRIETARY AND CONFIDENTIAL ISSUE 1 78 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 92
... Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is deasserted. PROPRIETARY AND CONFIDENTIAL ISSUE 1 79 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER -3 bit error rate. For AIS, ...
Page 93
... Due to the off-line nature of the DS3 Framer, PMON continues to accumulate performance meters even while the DS3-FRMR has declared OOF. PROPRIETARY AND CONFIDENTIAL ISSUE 1 80 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 94
... TDPR data link transmitter. The DS3-TRAN supports diagnostic modes in which it inserts parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, or all-zeros. PROPRIETARY AND CONFIDENTIAL ISSUE 1 81 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 95
... G.747 bit stream. The DS2 FRMR frames to a DS2 signal with a maximum average reframe time of less than 7 ms and frames to a G.747 signal with a maximum average reframe PROPRIETARY AND CONFIDENTIAL ISSUE 1 82 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 96
... FERF status in a valid state during an out of frame occurrence in DS2 mode, and ensures a better than 99.9% probability of freezing the valid status during an OOF occurrence in G.747 PROPRIETARY AND CONFIDENTIAL ISSUE 1 83 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 97
... When demultiplexing four DS1 streams from an M12 formatted DS2, the MX12 performs bit destuffing via interpretation of the C-bits. The MX12 also detects and indicates DS1 payload loopback requests encoded in the C-bits. As per PROPRIETARY AND CONFIDENTIAL ISSUE 1 84 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 98
... CAS or CCS H-MVIP and serial clock and data with CCS H-MVIP. Two Clock Master modes provide a serial clock and data egress interface with per link clocking provided by TECT3. The clock master modes are Clock Master: PROPRIETARY AND CONFIDENTIAL ISSUE 1 85 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 99
... E1 frame on a per-channel basis. The parity functions should not be enabled in NxChannel mode. PROPRIETARY AND CONFIDENTIAL ISSUE 1 T1-XB AS/E1-TR AN BasicTransm itte r: Frame G eneration, Alarm Insertio n, Signaling Insertion, Trunk C onditioning Line C oding 86 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Receive C LK[1:28] TJAT Transmit C LK[1:28] Digital PLL Transmit D ata[1:28] TRANSMITTER ...
Page 100
... T1 operation. PROPRIETARY AND CONFIDENTIAL ISSUE 1 T1-XBAS/E1-TRAN BasicTransm itter: Frame Gene ration, Alarm Insertion, Signaling Insertion, Trunk Co nditioning Line Coding 87 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Receive CLK[1:28] TJAT Transmit C LK[1 :28] Digital PLL Transmit D ata[1 :28] TRANSMITTER TRANSMITTER TJAT ...
Page 101
... ECLK[x]. PROPRIETARY AND CONFIDENTIAL ISSUE 1 T1-XBAS/E1-TRAN BasicTransm itter: Frame Gene ration, Alarm Insertion, Signaling Insertion, Trunk Co nditioning Line Coding 88 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER TRANSMITTER TJAT Digital PLL Transmit C LK[1 :28] TJAT FIFO Transmit D ata[1:28] TRANSMITTER TJAT ...
Page 102
... ECCSEN bit in the T1/E1 Egress Serial Interface Mode Select register is set to 0. PROPRIETARY AND CONFIDENTIAL ISSUE 1 T1-XB AS/E1-TRAN BasicTransm itter: Frame Gene ration, Alarm Insertion, Signaling Insertion, Trunk Co nditioning Line Coding 89 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER TRANSMITTER TJAT Transmit C LK[1:28] Digital PLL TJAT FIFO Transmit D ata[1:28] ...
Page 103
... T1s PROPRIETARY AND CONFIDENTIAL ISSUE 1 T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding 90 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER TRANSMITTER TJAT Transmit CLK[1:28] Digital PLL TJAT FIFO Transmit Data[1:28] ...
Page 104
... IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register. Clock Master: NxChannel and Clock Master: Full T1/E1 use the same IMODE[1:0] selection and are differentiated by the INXCHAN[1:0] bits in the same ragister as IMODE[1:0]. PROPRIETARY AND CONFIDENTIAL ISSUE 1 91 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 105
... Slip Bu ffer RA M FRM R Framer: Frame A lignmen t, Alarm Extraction FRAM Framer: Slip Bu ffer RA M FRM R Framer: Frame A lignmen t, Alarm Extraction 92 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER RECEIVER RJAT Receive Data[1:28] Digital Jitter Attenuator Receive CLK[1:28] RECEIVER RJAT Receive Data[1:28] Digita l Jitter ...
Page 106
... PROPRIETARY AND CONFIDENTIAL ISSUE 1 ELST Elastic FRAM Store Framer: Slip Buffer RA M FRM R Framer: Frame Alignment, Alarm Extraction 93 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER RECEIVER RJAT Receive Data[1:28] Digita l Jitter Attenuator Receive CLK[1:28] RECEIVER RJAT Receive Data[1:28] Digital Jitter ...
Page 107
... CAS bits while data transfer occurs over the PROPRIETARY AND CONFIDENTIAL ISSUE 1 ELST Elas tic FRAM Store Framer: Slip Bu ffer RA M FRMR Framer: Frame A lignmen t, Alarm Ext raction 94 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER RECEIVER RJAT Receive Data[1:28] Digita l Jitter Attenuator Receive CLK[1:28] ...
Page 108
... H-MVIP uses a Clock Slave serial interface, selected when PROPRIETARY AND CONFIDENTIAL ISSUE 1 ELST Elastic FRAM Store Framer: Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction 95 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER RECEIVER RJAT Receive Data[1:28] Digital Jitter Attenuator Receive CLK[1:28] ...
Page 109
... CLK52M. Using either reference clock frequency, the 44.736Mb/s rate is generated by gapping the reference clock in a fixed way. Timing adjustments are performed by adding or deleting four clocks over the 500uS period. PROPRIETARY AND CONFIDENTIAL ISSUE 1 96 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 110
... CAS bits from the SBISIPO and inserts them into the SBI bus structure. Note that ITU-T G.747 mutiplexed E1 streams are not supported over the SBI interface. The E1 mode of operation is restricted to using the serial clock and data or H-MVIP system interfaces. PROPRIETARY AND CONFIDENTIAL ISSUE 1 97 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 111
... TECT3. The Register Memory Map in Table 2 shows where the normal mode registers are accessed. The registers are organized so that backward software PROPRIETARY AND CONFIDENTIAL ISSUE 1 98 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 112
... Master Clock Monitor #1 0011H Master Clock Monitor #2 0012H Master Clock Monitor #3 0013H Master Clock Monitor #4 0014H Master Clock Monitor #5 0015H- Reserved 001FH 0020H Master Interrupt Source 0021H Master Interrupt Status T1/E1 #1-8 PROPRIETARY AND CONFIDENTIAL ISSUE 1 99 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 113
... T1/E1 Master Egress Serial Interface Mode Select 0087H T1/E1 Master Ingress Parity and Alarm Enable 0088H T1/E1 Master Egress Parity Enable 0089H T1/E1 Master Serial Interface Configuration 008AH T1/E1 Transmit Framing and Bypass Options PROPRIETARY AND CONFIDENTIAL ISSUE 1 100 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 114
... RXCE Ingress Data Link Bit Select 00A2H- RXCE Reserved 00A7H 00A8H TXCI Egress Data Link Control 00A9H TXCI Egress Data Link Bit Select 00AAH- TXCI Reserved 00AFH PROPRIETARY AND CONFIDENTIAL ISSUE 1 101 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 115
... RDLC Primary Address Match 00C5H RDLC Secondary Address Match 00C6H- Reserved 00C7H 00C8H TDPR Configuration 00C9H TDPR Upper Transmit Threshold 00CAH TDPR Lower Transmit Threshold 00CBH TDPR Interrupt Enable PROPRIETARY AND CONFIDENTIAL ISSUE 1 102 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 116
... RX- SIG-ELST Reserved 00E0H T1 ALMI Configuration 00E1H T1 ALMI Interrupt Enable 00E2H T1 ALMI Interrupt Status 00E3H T1 ALMI Alarm Detection Status 00E4H T1 XBOC Control 00E5H T1 XBOC Code 00E6H T1 RBOC Enable PROPRIETARY AND CONFIDENTIAL ISSUE 1 103 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 117
... E1 FRMR Maintenance/Alarm Status Interrupt Indication 00E6H E1 FRMR Framing Status 00E7H E1 FRMR Maintenance/Alarm Status 00E8H E1 FRMR International/National Bits 00E9H E1 FRMR CRC Error Count - LSB 00EAH E1 FRMR CRC Error Count - MSB PROPRIETARY AND CONFIDENTIAL ISSUE 1 104 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 118
... T1/E1 Framer Slice #3 01FFH 0200H- T1/E1 Framer Slice #4 027FH 0280H- T1/E1 Framer Slice #5 02FFH 0300H- T1/E1 Framer Slice #6 037FH 0380H- T1/E1 Framer Slice #7 03FFH 0400H- T1/E1 Framer Slice #8 047FH 0480H- T1/E1 Framer Slice #9 04FFH PROPRIETARY AND CONFIDENTIAL ISSUE 1 105 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 119
... T1 Framer Slice #22 0B7FH 0B00H T1/E1 Master Configuration 0B01H Reserved 0B02H T1/E1 Receive Options 0B03H T1/E1 Ingress Line Interface Configuration 0B04H T1/E1 Egress Line Interface Configuration 0B05H T1/E1 Master Ingress Serial Interface Mode Select PROPRIETARY AND CONFIDENTIAL ISSUE 1 106 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 120
... RX-ELST Idle Code 0B1BH RX-ELST Reserved 0B1CH TX-ELST Configuration 0B1DH TX-ELST Interrupt Enable/Status 0B1EH- TX-ELST Reserved 0B1FH 0B20H RXCE Ingress Data Link Control 0B21H RXCE Ingress Data Link Bit Select PROPRIETARY AND CONFIDENTIAL ISSUE 1 107 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 121
... PMON Reserved 0B3FH PMON Reserved 0B40H RDLC Configuration 0B41H RDLC Interrupt Control 0B42H RDLC Status 0B43H RDLC Data 0B44H RDLC Primary Address Match 0B45H RDLC Secondary Address Match PROPRIETARY AND CONFIDENTIAL ISSUE 1 108 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 122
... SIGX Channel Indirect Address/Control/ Change of Signaling State 0B5BH SIGX Channel Indirect Data Buffer/Change of Signaling State 0B5CH RX-SIG-ELST Configuration 0B5DH RX- SIG-ELST Interrupt Enable/Status 0B5EH RX- SIG-ELST Idle Code 0B5FH RX- SIG-ELST Reserved 0B60H T1 ALMI Configuration PROPRIETARY AND CONFIDENTIAL ISSUE 1 109 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 123
... T1 APRM One Second Content Octet 4 0B76H T1 APRM One Second Content MSB (Octet 5) 0B77H T1 APRM One Second Content LSB (Octet 6) 0B78H- Reserved 0B7FH 0B80H- T1 Framer Slice #23 0BFFH 0C00H- T1 Framer Slice #24 0C7FH PROPRIETARY AND CONFIDENTIAL ISSUE 1 110 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 124
... DS3 FRMR Configuration 100DH DS3 FRMR Interrupt Enable/Additional Configuration 100EH DS3 FRMR Interrupt Status 100FH DS3 FRMR Status 1010H DS3 PMON Performance Meters 1011H DS3 PMON Interrupt Enable/Status PROPRIETARY AND CONFIDENTIAL ISSUE 1 111 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 125
... DS3 RDLC Configuration 1029H DS3 RDLC Interrupt Control 102AH DS3 RDLC Status 102BH DS3 RDLC Data 102CH DS3 RDLC Primary Address Match 102DH DS3 RDLC Secondary Address Match PROPRIETARY AND CONFIDENTIAL ISSUE 1 112 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 126
... MX23 Loopback Request Detect 1046H MX23 Loopback Request Interrupt 1047H MX23 Reserved 1048H FEAC XBOC Control 1049H FEAC XBOC Code 104AH FEAC RBOC Configuration/Interrupt Enable 104BH FEAC RBOC Interrupt Status PROPRIETARY AND CONFIDENTIAL ISSUE 1 113 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 127
... MX12 #1 Loopback Interrupt 1075H- MX12 #1 Reserved 1077H 1078H- Reserved 107FH 1080H- DS2 FRMR #2 Registers 1087H 1088H- Reserved 108FH 1090H- MX12 #2 Registers 1097H 1098H- Reserved 109FH 10A0H- DS2 FRMR #3 Registers 10A7H PROPRIETARY AND CONFIDENTIAL ISSUE 1 114 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 128
... MX12 #5 Registers 10F7H 10F8H- Reserved 10FFH 1100H- DS2 FRMR #6 Registers 1107H 1108H- Reserved 110FH 1110H- MX12 #6 Registers 1117H 1118H- Reserved 111FH 1120H- DS2 FRMR #7 Registers 1127H 1128H- Reserved 112FH PROPRIETARY AND CONFIDENTIAL ISSUE 1 115 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 129
... INSBI FIFO Overrun Interrupt Status 1723H INSBI Tributary Register Indirect Access Address 1724H INSBI Tributary Register Indirect Access Control 1725H INSBI Reserved 1726H INSBI Tributary Control Indirect Access Data PROPRIETARY AND CONFIDENTIAL ISSUE 1 116 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 130
... INSBI Insert External ReSynch Interrupt Status 1733H- INSBI Reserved 173FH 1740H- SBI SIPO Reserved 175FH 1780H- SBI PISO Reserved 179FH 1780H- Reserved 1FFFH For all register accesses, CSB must be low. PROPRIETARY AND CONFIDENTIAL ISSUE 1 117 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 131
... Writing into read-only normal mode register bit locations does not affect TECT3 operation unless otherwise noted. The register descriptions are contained in a separate TECT3 register description document. PROPRIETARY AND CONFIDENTIAL ISSUE 1 118 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 132
... Writeable register bits are not initialized upon reset unless otherwise noted. PROPRIETARY AND CONFIDENTIAL ISSUE 1 119 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 133
... When IOTST is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate PROPRIETARY AND CONFIDENTIAL ISSUE 1 Function Default Unused X Unused X Unused X PMCTST X DBCTRL X IOTST X HIZDATA X HIZIO X 120 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 134
... Boundary Scan IDCODE Identification SAMPLE Boundary Scan BYPASS Bypass BYPASS Bypass STCTEST Boundary Scan BYPASS Bypass BYPASS Bypass PROPRIETARY AND CONFIDENTIAL ISSUE 1 Instruction Code IR[2:0] 000 001 010 011 100 101 110 111 121 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 135
... ECLK[12]_OEN PROPRIETARY AND CONFIDENTIAL ISSUE 1 32 bits 3H 8315 0CDH 383150CDH Register Bit 122 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - ...
Page 136
... Register Bit 123 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL ...
Page 137
... Register Bit 124 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. IN_CELL - IN_CELL - IN_CELL - OUT_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - IN_CELL - OUT_CELL - OUT_CELL ...
Page 138
... Register Bit 125 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. OUT_CELL - IN_CELL - OUT_CELL - IO_CELL - IN_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL ...
Page 139
... PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL ...
Page 140
... PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. IN_CELL - IN_CELL - IN_CELL - IN_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - IO_CELL ...
Page 141
... PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - OUT_CELL ...
Page 142
... PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL ...
Page 143
... PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL ...
Page 144
... PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL ...
Page 145
... Register Bit 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 132 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Cell Type Device I.D. OUT_CELL 0 OUT_CELL 1 OUT_CELL 0 IN_CELL 1 IN_CELL 0 IN_CELL 0 OUT_CELL 0 IO_CELL 1 ...
Page 146
... STANDARD PRODUCT DATASHEET PMC-2011596 3. Enable cell HIZ, tristates all pins that do not have an individual pinname_OEN enable signal. PROPRIETARY AND CONFIDENTIAL ISSUE 1 133 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 147
... 134 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 84 bits 84 bits 84 bits ...
Page 148
... FEBEs on the C-bits in M-subframes 3 and 4 are reported in the DS3 PMON Path Parity Error Event Count and FEBE Event Count registers respectively. The path maintenance datalink signal is extracted by theDS3 RDLC HDLC receiver (if enabled). PROPRIETARY AND CONFIDENTIAL ISSUE 1 135 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 149
... The BER at which the probability of counter saturation reaches 50% is shown for various counters in Table 6 for E1 mode, and in Table 7 for T1 mode. PROPRIETARY AND CONFIDENTIAL ISSUE 1 136 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 150
... Figure 28 illustrates the expected count values for a range of Bit Error Ratios in E1 mode. PROPRIETARY AND CONFIDENTIAL ISSUE 1 -3 Format BER - ESF - ESF cannot saturate -3 , the average counter event count 137 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 151
... BER. This must be taken into account æ ö æ 8 ö ç - ÷ log ç 1 CRCE ÷ ç 8000 ÷ è ø ç ÷ 256 ç ç ÷ ÷ è ø 138 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 200 250 - each CRC-4 error is often , ...
Page 152
... CRCE Average Count Over Many 1 Second Intervals 0 50 100 150 Framing Bit Error Count Per Second -4 , each CRC-6 error is often due to more than one 139 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 800 1000 1200 200 250 -4 , there tends ...
Page 153
... CRCE Average Count Over Many 1 Second Intervals 200 400 600 800 Bit Error Event Count Per Second 140 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 300 350 1000 1200 ...
Page 154
... TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The PROPRIETARY AND CONFIDENTIAL ISSUE 1 141 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 155
... Abort sequence and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To re-enable the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register should be written with any value. PROPRIETARY AND CONFIDENTIAL ISSUE 1 142 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 156
... The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. The following procedure should be followed to transmit HDLC packets: PROPRIETARY AND CONFIDENTIAL ISSUE 1 143 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 157
... When the first flag is found, an interrupt will be generated, and a dummy byte will be written into the FIFO buffer. This is done to provide alignment of link up status with the data read from the PROPRIETARY AND CONFIDENTIAL ISSUE 1 144 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 158
... If COLS = 1, then set the EMPTY FIFO software flag PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO PROPRIETARY AND CONFIDENTIAL ISSUE 1 145 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 159
... If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt. PROPRIETARY AND CONFIDENTIAL ISSUE 1 146 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 160
... A - abort sequence (01111111 packet data bytes INT - active high interrupt output FE - internal FIFO empty status LA - state of the LINK ACTIVE software flag 147 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER data bytes received and transferred to the FIFO Buffer ...
Page 161
... Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit PROPRIETARY AND CONFIDENTIAL ISSUE 1 FLAG SAPI TEI CONTROL 148 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER C ...
Page 162
... Data for Previous Second(T'-1) Data for earlier Second(T'-2) Data for earlier Second(T'-3) CRC16 Frame Check Sequence Closing LAPD flag Interpretation CRC ERROR EVENT =1 1<CRC ERROR EVENT £5 5<CRC ERROR EVENT £10 149 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 163
... Severely Errored Framing Event ³ 1(FE shall =0) Frame Synchronization Bit Error Event ³1 (SE shall=0 ) Line code violation event ³ 1 Slip Event ³ 1 Payload Loopback Activated Under Study For Synchronization. Reserved ( Default Value =0) One second Report Modulo 4 Counter 150 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 164
... The system Diagnostic Digital loopback can be initiated at any time by the system via the µP interface to check the path of system data through PROPRIETARY AND CONFIDENTIAL ISSUE 1 151 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 165
... Line Coding FRAM Framer/ ELST Slip Buffer Elastic RAM Store T1/E1-FRMR Framer: Frame Alignment, Alarm Extraction 152 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER TRANSMITTER TOPS TJAT TxCLK[1:28] Digital Jitter TxD[1:28] Attenuator oopback RJAT RxCLK[1:28] Digital Jitter RxD[1:28] Attenuator ...
Page 166
... Di agn ost i c Loopb ack FRAM Framer/ ELST Slip Buffer Elastic RAM Store T1/E1-FRMR Framer: Frame Alignment, Alarm Extraction 153 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER TRANSMITTER TOPS TJAT TxCLK[1:28] Digital Jitter TxD[1:28] Attenuator RJAT RxCLK[1:28] Digital Jitter RxD[1:28] Attenuator ...
Page 167
... Per - DS0 Loopback FRAM Framer/ ELST Slip Buffer Elastic RAM Store T1/E1-FRMR Framer: Frame Alignment, Alarm Extraction 154 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER TRANSMITTER TOPS Timing Options TJAT TxCLK[1:28] Digital Jitter TxD[1:28] Attenuator RJAT RxCLK[1:28] Digital Jitter RxD[1:28] ...
Page 168
... PLOOP bit in the same register. PROPRIETARY AND CONFIDENTIAL ISSUE 1 DS3 FRMR MX23 DS3 R R TRAN M R 155 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER F MX12 # MX12 # MX12 # MX12 #4 ...
Page 169
... TMFP . PROPRIETARY AND CONFIDENTIAL ISSUE 1 DS3 FRMR MX23 DS3 R R TRAN M R MX23 Optional DEMUX AIS Insertion 156 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER F MX12 # MX12 # MX12 # MX12 # MX12 #3 ...
Page 170
... SPE1 carries the T1s numbered 1,1 through 1,28 or DS3 number 1,1. SPE2 carries T1s numbered 2,1 through 2,28 or DS3 number 2,1. SPE3 carries T1s numbered 3,1 through 3,28 or DS3 number 3,1. The most significant bit in all formats is the first bit of transmission. PROPRIETARY AND CONFIDENTIAL ISSUE 1 157 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 171
... SPE1SPE2SPE3SPE1 ··· SPE1SPE2SPE3 - - - - SPE1SPE2SPE3SPE1 7,35,63 8,36,64 34,62,90 158 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 268 269 270 SPE1SPE2SPE3 SBI Column 19,103,187 20,104,188 7,35,63 21,105,189 22,106,190 23,107,191 100,184,268 101,185,269 34,62,90 102,186,270 ...
Page 172
... When detected by the Link Layer it will retard the channel by leaving the octet following the next octet unused. Both advance and retard rate adjustments take place in the frame or multi-frame following the justification request. PROPRIETARY AND CONFIDENTIAL ISSUE 1 159 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 173
... Fast PROPRIETARY AND CONFIDENTIAL ISSUE 1 · · · · · · · · · ß Clock Count Bit # 7 6 ALM 0 ClkRate[1:0] T1 Clocks / 2KHz 772 773 160 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER à ß Phase 5:4 3:0 Phase[3:0] à ...
Page 174
... Link Rate Octet. In the egress direction the TECT3 can be configured to use the alarm bit to force AIS on a per link basis. PROPRIETARY AND CONFIDENTIAL ISSUE 1 771 Bit # ClkRate[1:0] DS3 Clocks / 2KHz 22368 22372 22364 161 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 5:4 3:0 Unused ...
Page 175
... Unused DS0#13 7 Unused DS0#16 8 Unused DS0#19 PROPRIETARY AND CONFIDENTIAL ISSUE 1 T1#2,1-3,28 T1#1,1 T1#2,1-3,28 19 20-102 103 104-186 DS0#2 - DS0#5 - DS0#8 - DS0#11 - DS0#14 - DS0#17 - DS0#20 162 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER T1#1,1 T1#2,1-3,28 187 188-270 - PPSSSSFR - - DS0 DS0 DS0 DS0# DS0# DS0# DS0#21 - ...
Page 176
... DS0#20 - DS0# DS0#2 - DS0#5 - DS0#8 - DS0#11 - DS0#14 - DS0#17 - DS0#20 - DS0#23 P and bits. Channel associated signaling 163 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER - DS0# PPSSSSFR - - DS0 DS0 DS0 DS0# DS0# DS0# DS0# DS0# PPSSSSFR ...
Page 177
... M8 10 C16 C20 C24 M10 D12 F5 M11 11 D16 D20 F6 M12 11 D24 phase alignment bits, due to possible frame slips at the 1 0 164 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER bits (i.e. in either 1 0 ...
Page 178
... DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 V5 DS3 DS3 DS3 DS3 DS3 165 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER DS3 Col 85 268 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 ...
Page 179
... Number 0-3 Undefined 4-7 1 8-11 2 12-15 3 16-19 Undefined PROPRIETARY AND CONFIDENTIAL ISSUE 8*I 8*I 8*I 8*I 8*I 8*B 5*R 8*B 5*R 8*B 8*B 5*R 8*B 5*R 8*B 8*B 5*R 8*B 5*R 8*B 8*B 5*R 8*B 5*R 8*B 8*B 5*R 8*B 5*R 8*B 8*B 5*R 8*B 5*R 8*B Second T1 DS0 Number Undefined Undefined 166 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 8*I 8*I 8*I 8*I 8*I 5*R 8*B 5*R 8*B 5*R 5*R 8*B 5*R 8*B 5*R 5*R 8*B 5*R 8*B 5*R 5*R 8*B 5*R 8*B 5*R 5*R 8*B 5*R 8*B 5*R 5*R 8*B 5*R 8*B 5*R Third T1 DS0 Fourth T1 DS0 Number Number Undefined Undefined Undefined Undefined 8*B 8*B 8*B 8*B ...
Page 180
... Undefined · · · 21 Undefined Second E1 TS Number · · · 167 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Undefined Undefined · · · · · · Undefined Undefined ...
Page 181
... Table 25: CCS E1 H-MVIP Format in G.747 Mode H-MVIP Timeslot Number PROPRIETARY AND CONFIDENTIAL ISSUE 1 T1 Number · · · undefined undefined · · · undefined E1 Number E1 Number undefined 4 168 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER E1 Number ...
Page 182
... PROPRIETARY AND CONFIDENTIAL ISSUE undefined · · · undefined · · · undefined 169 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER undefined · · · 21 undefined · · · undefined 1 2 ...
Page 183
... Figure 41 below: PROPRIETARY AND CONFIDENTIAL ISSUE 1 th through 28 framer blocks are not used in this mode and 28 170 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 3 undefined · · · 21 undefined · · · undefined th framer blocks are not used in ...
Page 184
... PRGD update, setting PDR[1: the PRGD Control register, and reading the Pattern Detector registers (which will then contain the 32 bits detected immediately prior to the strobe). PROPRIETARY AND CONFIDENTIAL ISSUE 1 LENGTH PS TAP 2 3 171 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 32 ...
Page 185
... The PRGD can be configured to monitor the standardized pseudo random and repetitive patterns described in ITU-T O.151. The register configurations required to generate these patterns and others are indicated in Table 26 and Table 27 below: PROPRIETARY AND CONFIDENTIAL ISSUE 1 172 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 186
... 173 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER IR#3 IR#4 TINV RINV ...
Page 187
... IR 174 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER IR#2 IR#3 IR#4 TINV RINV ...
Page 188
... Figure 42: Boundary Scan Architecture TDI TMS Test Access Port Controller TRSTB TCK PROPRIETARY AND CONFIDENTIAL ISSUE 1 Boundary Scan Register Device Identification Register Bypass Register Instruction Register and Decode Control Select Tri-state Enable 175 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Mux DFF TDO ...
Page 189
... The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below. PROPRIETARY AND CONFIDENTIAL ISSUE 1 176 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 190
... PROPRIETARY AND CONFIDENTIAL ISSUE 1 1 Select-DR-Scan 0 1 Capture-DR 0 Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- All transitions dependent on input TMS 177 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 1 Select-IR-Scan 0 1 Capture-IR 0 Shift- Exit1-IR 0 Pause- Exit2-IR 1 Update- ...
Page 191
... The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. PROPRIETARY AND CONFIDENTIAL ISSUE 1 178 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 192
... Shift-DR state. IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. PROPRIETARY AND CONFIDENTIAL ISSUE 1 179 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER ...
Page 193
... Scan Register table in the JTAG Test Port section 11.2. Figure 44: Input Observation Cell (IN_CELL) IDCODE Input Pad SHIFT-DR I.D. Code bit CLOCK-DR Scan Chain In PROPRIETARY AND CONFIDENTIAL ISSUE MUX 180 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Scan Chain Out INPUT to internal logic ...
Page 194
... G1 1 MUX MUX Scan Chain Out MUX 181 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER Scan Chain Out OUTPUT or Enable D C INPUT to internal logic G1 1 OUTPUT MUX 1 to pin D C ...
Page 195
... Figure 47: Layout of Output Enable and Bidirectional Cells OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic PROPRIETARY AND CONFIDENTIAL ISSUE 1 Scan Chain Out OUT_CELL IO_CELL Scan Chain In 182 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER I/O PAD ...
Page 196
... The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV. PROPRIETARY AND CONFIDENTIAL ISSUE 1 3 consec 0s INFO 84 INFO 84 X2 BIT BIT 183 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER LCV C BIT INFO 1 INFO 2 INFO 3 INFO 4 LCV INDICATION ...
Page 197
... Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals. PROPRIETARY AND CONFIDENTIAL ISSUE Nib 1 Nib 21 X1 Bit 4 Bit 1 184 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER 1 0 Nib 22 Nib 1190 Nib Bit 4 Bit 1 Bit 4 ...
Page 198
... TICLK or TGAPCLK for sampling TDATI. PROPRIETARY AND CONFIDENTIAL ISSUE 1 X1 INFO 84 F4 INFO 82 INFO 83 INFO 84 INFO 1 INFO 83 INFO 84 INFO 1 INFO 2 INFO 3 185 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER X2 INFO 82 INFO 2 INFO 1 INFO 2 INFO 3 INFO 1 INFO 2 INFO 3 INFO 4 INFO 81 ...
Page 199
... INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO 186 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER X INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO 84 1 ...
Page 200
... H3 H3 ··· ··· ··· ··· 187 PM4328 TECT3 HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER DS0#4. V5 DS0#9. H3 DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1 ...