PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 100

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
Figure 15: Clock Master: Clear Channel
Clock Master: Clear Channel mode has no frame alignment therefore no frame
alignment is indicated to the upstream device. ECLK[x] is a continuous clock at
1.544Mb/s for T1 links or 2.048Mb/s for E1 links.
Figure 16: Clock Slave: EFP Enabled
In Clock Slave: EFP Enabled mode, the egress interface is clocked by the
common egress clock, CECLK. The transmitter is either frame-aligned or
superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP
bit in the Master Egress Slave Mode Serial Interface Configuration register.
EFP[x] is configurable to indicate the frame alignment or the superframe
alignment of ED[x]. CECLK can be enabled to be either a 1.544 MHz clock for
T1 links or a 2.048 MHz clock for T1 and E1 links. The CECLK2M bit in the
Master Egress Slave Mode Serial Interface Configuration register selects the
2.048MHz clock for T1 operation.
Inputs Tim ed
to CEC LK
ED[x] Tim ed
to ECLK[x]
EC LK[1:28]
EFP[1:28]
ED[1:28]
ED[1:28]
CECLK
C TCLK
CEFP
Inte rface
Inte rface
System
System
Egress
Egress
ESIF
ESIF
ISSUE 1
T1-XBAS/E1-TRAN
Frame Gene ration,
Signaling Insertion,
Trunk Co nditioning
BasicTransm itter:
Alarm Insertion,
Line Coding
87
Digital PLL
Digital PLL
TJAT
TJAT
TJAT
FIFO
TRANSMITTER
TRANSMITTER
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3
Transmit C LK[1 :28]
Transmit C LK[1 :28]
Receive CLK[1:28]
Transmit D ata[1 :28]
Transmit D ata[1:28]