PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 101

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
Figure 17: Clock Slave: External Signaling
In Clock Slave: External Signaling mode, the egress interface is clocked by the
common egress clock, CECLK. The transmitter is either frame-aligned or
superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP
bit in the Master Egress Slave Mode Serial Interface Configuration register. The
ESIG[x] signal contains the robbed-bit signaling data to be inserted into Transmit
Data[x], with the four least significant bits of each channel on ESIG[x]
representing the signaling state (ABCD or ABAB in T1 SF mode). EFP[x] is not
available in this mode.
Figure 18: Clock Slave: Clear Channel
In Clock Slave: Clear Channel mode, the egress interface is clocked by the
externally provided egress clock, ECLK[x]. ECLK[x] must be a 1.544 MHz clock
for T1 links or a 2.048 MHz clock for E1 links. In this mode the T1/E1 framers are
bypassed except for the TJAT which may or may not be bypassed depending on
the setting of the TJATBYP bit in the T1/E1 Egress Line Interface Options
register. Typically the TJAT would be bypassed unless jitter attenuation is
required on ECLK[x].
Inputs Tim ed
to CEC LK
Input Tim ed
to ECLK[x]
ECLK[1:28]
ESIG[1:28 ]
ED[1:28]
ED[1:28]
CECLK
CEFP
Inte rface
Inte rface
System
System
Egress
Egress
ESIF
ESIF
ISSUE 1
T1-XBAS/E1-TRAN
Frame Gene ration,
Signaling Insertion,
Trunk Co nditioning
BasicTransm itter:
Alarm Insertion,
Line Coding
88
Digital PLL
Digital PLL
TJAT
TJAT
TJAT
TJAT
FIFO
FIFO
TRANSMITTER
TRANSMITTER
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3
Transmit C LK[1 :28]
Transmit C LK[1 :28]
Transmit D ata[1:28]
Transmit D ata[1:28]