PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 165

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PM4328-PI

Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet

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STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
ECLK[1:28]/EFP[1:28]/
ICLK[1:28]/ISIG[1:28]
the framer. The payload can also be looped-back on a per-DS0 basis to allow
network testing without taking an entire DS1 off-line.
T1/E1 Line Loopback
T1/E1 Line loopback is initiated by setting the LLOOP bit to a 1 in the T1/E1
Diagnostics register (000DH + N*80H, N=1 to 28). When in line loopback mode
the appropriate T1/E1 framer in the TECT3 is configured to internally connect the
jitter-attenuated clock and data from the RJAT to the transmit clock and data
(shown as TxD[x] and TxCLK[x] in the lineloopback diagram) going to the M13
mux. The RJAT may be bypassed if desired. Conceptually, the data flow
through a single T1/E1 framer in this loopback condition is illustrated in Figure
35.
Figure 35: T1/E1 Line Loopback
T1/E1 Diagnostic Digital Loopback
When Diagnostic Digital loopback is initiated, by writing a 1 to the DLOOP bit in
the T1/E1 Diagnostics register (000DH + N*80H, N=1 to 28), the appropriate
T1/E1 framer in the TECT3 is configured to internally connect its transmit clock
and data (shown as TxD[x] and TxCLK[x] in the diagnostic loopback figure) to the
ESIG[1:28]
IFP[1:28]
ED[1:28]
CTCLK*
CECLK*
ID[1:28]
CICLK*
CEFP*
CIFP*
Interface
Interface
Egress
Ingress
ESIF
ISIF
ISSUE 1
Elastic
ELST
Store
T1-XBAS/E1-TRAN
Frame Generation,
Signaling
Trunk Conditioning
I
152
BasicTransmitter:
Alarm Insertion,
Line Coding
ti
T1/E1-FRMR
Slip Buffer
Alignment,
Extraction
Framer/
FRAM
Framer:
Frame
RAM
Alarm
Timing Options
Digital Jitter
Attenuator
HIGH DENSITY T1/E1 FRAMER
TOPS
TJAT
Digital Jitter
Attenuator
RJAT
AND M13 MULTIPLEXER
TRANSMITTER
Li ne L oopback
PM4328 TECT3
RECEIVER
TxCLK[1:28]
TxD[1:28]
RxCLK[1:28]
RxD[1:28]

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