PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 179

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PM4328-PI

Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet

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STANDARD PRODUCT
DATASHEET
PMC-2011596
12.11 H-MVIP Data Format
PROPRIETARY AND CONFIDENTIAL
Table 20: DS3 Block Format
Table 21: DS3 Multi-frame Stuffing Format
DS3 asynchronous timing is compensated via the H3 octet. DS3 link rate
adjustments are optionally passed across the SBI via the Linkrate octet.
The H-MVIP data and Channel Associated Signaling interfaces on the TECT3
are able to carry all the DS0s for 28 T1s or all timeslots for 21 E1s. When
Carrying timeslots from E1s the H-MVIP frame is completely filled with 128
timeslots from four E1s but when carrying DS0s from four T1s there are not
enough DS0s to completely fill the 128 byte frame. Table 22 shows how the
DS0s and CAS bits of four T1s are formatted in the 128 timeslot H-MVIP frame.
Table 23 shows the timeslot and CAS bit H-MVIP format when in G.747 mode.
The CAS bits are carried in bits 5,6,7 and 8 of each byte on the CASID[1:7] and
CASED[1:7] H-MVIP buses.
Table 22: Data and CAS T1 H-MVIP Format
Timeslot
Number
0-3
4-7
8-11
12-15
16-19
V5
V5
V5
V5
V5
V5
Octet #
Data
4*R
4*R
4*R
4*R
4*R
5*R
8*B
8*B
8*B
8*B
8*B
8*B
RRRFIIII
First T1 DS0
Undefined
Undefined
1
Number
5*R
5*R
5*R
5*R
5*R
5*R
1
2
3
ISSUE 1
8*B
8*B
8*B
8*B
8*B
8*B
8*I
2
5*R
5*R
5*R
5*R
5*R
5*R
8*I
3
Second T1 DS0
Undefined
Undefined
Number
8*B
8*B
8*B
8*B
8*B
8*B
8*I
4
1
2
3
5*R
5*R
5*R
5*R
5*R
5*R
8*I
166
5
8*B
8*B
8*B
8*B
8*B
8*B
8*I
6
Third T1 DS0
5*R
5*R
5*R
5*R
5*R
5*R
8*I
7
Undefined
Undefined
Number
8*B
8*B
8*B
8*B
8*B
8*B
1
2
3
8*I
8
5*R
5*R
5*R
5*R
5*R
5*R
8*I
9
HIGH DENSITY T1/E1 FRAMER
8*B
8*B
8*B
8*B
8*B
8*B
8*I
10
Fourth T1 DS0
AND M13 MULTIPLEXER
Undefined
Undefined
Number
PM4328 TECT3
5*R
5*R
5*R
5*R
5*R
5*R
8*I
11
1
2
3
8*B
8*B
8*B
8*B
8*B
8*B

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