PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 206

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
CECLK
EFP[x]
CEFP
ED[x]
CECLK
EFP[x]]
CEFP
ED[x]
Figure 68: T1 Egress Interface 2.048 MHz Clock Slave: EFP Enabled Mode
The Egress Interface is configured for the Clock Slave: EFP Enabled Mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
The 2.048 MHz internally gapped clock mode is selected by writing CECLK2M to
logic 1 in the Master Egress Slave Mode Serial Interface register. In Figure 68,
CEFP is configured for superframe alignment by writing CEMFP to logic 1 in the
Master Egress Slave Mode Serial Interface register, so that the CEFP input must
pulse once every 12 or 24 frames (for SF and ESF, respectively) on the first F-bit
of the multiframe to specify superframe alignment, instead of once every frame
to specify frame alignment. If parity checking is enabled, a parity bit should be
inserted on ED[x] in the first bit of each frame. The EFP[x] output will pulse high
to mark the F-bit of each frame in order to indicate frame alignment to an
upstream device. EFP[x] may be configured to mark superframe alignment
instead by setting the EMFP bit in the T1/E1 Serial Interface Configuration
register. The values of the don’t-care bits are not important, except that they will
be used in the backplane parity check if it is enabled.
F-Bit or
Parity
F
Ch24
Don't Care
1 2 3 4 5 6 7 8
Ch1
Channel 1
Frame 1
ISSUE 1
Ch2
Ch3
1 2 3 4 5 6 7 8
Channel 2
Frame 1
Ch4
193
Ch5
1 2 3 4 5 6 7 8
Channel 3
Frame 1
Ch6
Ch7
"filler"
Don't Care
HIGH DENSITY T1/E1 FRAMER
Ch23
AND M13 MULTIPLEXER
Ch24
1 2 3 4 5 6 7 8
PM4328 TECT3
Channel 4
Frame 1
Ch1