PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 211

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
ISIG[x]
CICLK
CIFP
ID[x]
ISIG[x]
CICLK
CIFP
ID[x]
Figure 78: T1 Ingress Interface 2.048 MHz Clock Slave: External Signaling
Mode
The Ingress Interface is programmed for Clock Slave mode by setting the
IMODE[1:0] in the T1/E1 Ingress Serial Interface Mode Select register. The
2.048 MHz internally-gapped clock mode is selected by setting the CICLK2M bit
to logic 1 in the Master Ingress Slave Mode Serial Interface Configuration
register. ID[x] is timed to the active edge of CICLK, and is frame-aligned to CIFP.
CIFP need not be provided every frame. ID[x] and ISIG[x] may be configured to
carry a parity bit during the first bit of each frame. The values of the filler bits will
depend on the exact configuration of the TECT3, and they will be included in the
parity calculation.
or Parity
F-Bit
F
Ch24
Don't Care
Don't Care
1 2 3 4 5 6 7 8
Ch1
Channel 1
Ch2
ISSUE 1
A B C D
Ch3
1 2 3 4 5 6 7 8
Channel 2
A B C D
Ch4
198
Ch5
1 2 3 4 5 6 7 8
Channel 3
Ch6
A B C D
Ch7
Don't Care
"filler"
Don't Care
Ch23
HIGH DENSITY T1/E1 FRAMER
Ch 24
1 2 3 4 5 6 7 8
AND M13 MULTIPLEXER
Channel 4
PM4328 TECT3
A B C D
Ch1