PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 243

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PM4328-PI

Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet

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STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
Table 48: Transmit Line Interface Timing (Figure 98)
Figure 98: Transmit Line Interface Timing
Notes on Ingress and Egress Serial Interface Timing:
1. CECLK and CICLK can be gapped and/or jittered clock signals subject to the
2. Guaranteed by design for nominal XCLK input frequency (37.056 MHz ±100
3. CTCLK can be a jittered clock signal subject to the minimum high and low
4. High pulse width is measured from the 1.4 Volt points of the rise and fall
Symbol
t H CTCLK
t L CTCLK
minimum high and low times shown. These specifications correspond to
nominal XCLK input frequencies.
ppm for T1 modes and 49.152 MHz ±50ppm for E1 modes).
times shown. These specifications correspond to nominal XCLK input
frequency of 37.056 MHz ±100 ppm for T1 modes and 49.152 MHz ±50ppm
for E1 modes.
ramps. Low pulse width is measured from the 1.4 Volt points of the fall and
rise ramps.
CTCLK
Description
CTCLK Frequency (when used for TJAT
REF), typically 1.544 MHz± 130 ppm for
T1 operation or 2.048 MHz± 50 ppm for E1
operation
CTCLK High Duration
TJAT REF)
CTCLK Low Duration
TJAT REF)
ISSUE 1
2,3,6
t
L
CTCLK
t
H
CTCLK
4
4
(when used for
(when used for
230
t
CTCLK
Min
1.5
100
100
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Max
2.1
PM4328 TECT3
Units
MHz
ns
ns

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