PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 54

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
Pin Name
CASED[4]
CASED[5]
CASED[6]
CASED[7]
CCSED
PROPRIETARY AND CONFIDENTIAL
Type
Input
ISSUE 1
Pin
No.
M22
M1
E22
L2
P1
Function
DS0s or E1 timeslots. Each CASED[x] signal carries
CAS for four complete T1s or E1s formatted according
to the H-MVIP standard. CASED[x] carries the
corresponding CAS values of the channel data carried
in MVED[x].
CASED[x] is aligned to the common H-MVIP
16.384Mb/s clock, CMV8MCLK, frame pulse clock,
CMVFPC, and frame pulse, CMVFPB. CASED[x] is
sampled on every second rising or falling edge of
CMV8MCLK as fixed by the common H-MVIP frame
pulse clock, CMVFPC. The sampling edge of
CMV8MCLK is selected via the CMVEDE bit in the
Master Common Ingress Serial and H-MVIP Interface
Configuration register.
CASED[1:7] shares the same pins as
ED[2,6,10,14,18,22,26].
Common Channel Signaling Egress Data (CCSED).
In T1 mode CCSED carries the 28 common channel
signaling channels to be transmitted in each of the 28
T1s. In E1 mode CCSED carries up to 3 timeslots
(15,16, 31) to be transmitted in each of the 21 E1s.
CCSED is formatted according to the H-MVIP
standard.
CCSED is aligned to the common H-MVIP 16.384Mb/s
clock, CMV8MCLK, frame pulse clock, CMVFPC, and
frame pulse, CMVFPB. CCSED is sampled on every
second rising or falling edge of CMV8MCLK as fixed
by the common H-MVIP frame pulse clock, CMVFPC.
The sampling edge of CMV8MCLK is selected via the
CMVEDE bit in the Master Common Ingress Serial and
H-MVIP Interface Configuration register.
41
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3