PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 84

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
9.18 Receive and Transmit Digital Jitter Attenuator (RJAT, TJAT)
PROPRIETARY AND CONFIDENTIAL
The Digital Jitter Attenuation function is provided by the DJAT blocks. Each
framer in the TECT3 contains two separate jitter attenuators, one between the
receive demultiplexed or demapped T1 or E1 link and the ingress interface
(RJAT) and the other between the egress interface and the transmit T1 or E1 link
to be multiplexed into DS3 (TJAT). Each DJAT block receives jittered data and
stores the stream in a FIFO timed to the associated receive jittered clock. The
jitter attenuated data emerges from the FIFO timed to the jitter attenuated clock.
In the RJAT, the jitter attenuated clock (ICLK[x]) is referenced to the
demultiplexed tributary receive clock. In the TJAT, the jitter attenuated transmit
tributary clock feeding the M13 multiplexer may be referenced to either CTCLK,
CECLK, or the tributary receive clock.
In T1 mode each jitter attenuator generates its output clock by adaptively dividing
the 37.056 MHz XCLK signal according to the phase difference between the jitter
attenuated clock and the input reference clock. Jitter fluctuations in the phase of
the reference clock are attenuated by the phase-locked loop within each DJAT
so that the frequency of the jitter attenuated clock is equal to the average
frequency of the reference. To best fit the jitter attenuation transfer function
recommended by TR 62411, phase fluctuations with a jitter frequency above 6.6
Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase
fluctuations with frequencies below 6.6 Hz are tracked by the jitter attenuated
clock. The jitter attenuated clock (ICLK[x] for the RJAT and transmit clock for the
TJAT) are used to read data out of the FIFO.
In E1 mode each jitter attenuator generates the jitter-free 2.048 MHz output
clock by adaptively dividing the 49.152 MHz XCLK signal according to the phase
difference between the jitter attenuated clock and input reference clock.
Fluctuations in the phase of the input data clock are attenuated by the phase-
locked loop within DJAT so that the frequency of the jitter attenuated clock is
equal to the average frequency of the input data clock. Phase fluctuations with a
jitter frequency above 8.8 Hz are attenuated by 6 dB per octave of jitter
frequency. Wandering phase fluctuations with frequencies below 8.8 Hz are
tracked by the jitter attenuated clock. To provide a smooth flow of data out of
DJAT, the jitter attenuated clock is used to read data out of the FIFO.
The TJAT and RJAT have programmable divisors in order to generate the jitter
attenuated clock from the various reference sources. The divisors are set using
the TJAT and RJAT Jitter Attenuator Divider N1 and N2 registers. The following
formula must be met in order to select the values of N1 and N2:
Fin/(N1 + 1) = Fout/(N2 + 1)
ISSUE 1
71
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3