PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 90

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
9.19 Timing Options (TOPS)
9.20 Pseudo Random Binary Sequence Generation and Detection (PRBS)
9.21 Pseudo Random Pattern Generation and Detection (PRGD)
PROPRIETARY AND CONFIDENTIAL
Frequency Range
In the non-attenuating mode for T1 rates, that is, when the FIFO is within one UI
of overrunning or under running, the tracking range is 1.48 to 1.608 MHz. The
guaranteed linear operating range for the jittered input clock is 1.544 MHz ± 200
Hz with worst case jitter (29 UIpp) and maximum XCLK frequency offset (± 100
ppm). The nominal range is 1.544 MHz ± 963 Hz with no jitter or XCLK
frequency offset.
In the non-attenuating mode for E1 rates the tracking range is 1.963 to 2.133
MHz. The guaranteed linear operating range for the jittered input clock is 2.048
MHz ± 1278 Hz with worst case jitter (42 UIpp) and maximum XCLK frequency
offset (± 100 ppm).
The Timing Options block provides a means of selecting the source of the
internal input clock to the TJAT block, the reference clock for the TJAT digital
PLL, and the clock source used to derive the transmit clock to the M13 mux.
The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a
software selectable PRBS generator and checker for 2
polynomials for use in the T1 and E1 links. PRBS patterns may be generated in
either the transmit or receive directions, and detected in the opposite direction.
The PRBS block can perform an auto synchronization to the expected PRBS
pattern and accumulates the total number of bit errors in two 24-bit counters.
The error count accumulates over the interval defined by to the Global PMON
Update Register. When an accumulation is forced, the holding register is
updated, and the counter reset to begin accumulating for the next interval. The
counter is reset in such a way that no events are missed. The data is then
available in the Error Count registers until the next accumulation.
The Pseudo Random Pattern Generator/Detector (PRGD) block is a software
programmable test pattern generator, receiver, and analyzer for the DS3
payload. Patterns may be generated in the transmit direction, and detected in
the receive direction. Two types of ITU-T O.151 compliant test patterns are
provided : pseudo-random and repetitive.
ISSUE 1
77
11
-1, 2
15
-1 or 2
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
20
PM4328 TECT3
-1 PRBS