CC2500

Manufacturer Part NumberCC2500
DescriptionLow Cost, Low-power 2.4 Ghz Rf Transceiver Designed For Low-power Wireless Apps In 2.4 Ghz Ism Band
ManufacturerTexas Instruments Incorporated
CC2500 datasheet
 


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CC2500
Low-Cost Low-Power 2.4 GHz RF Transceiver
Applications
• 2400-2483.5 MHz ISM/SRD band systems
• Consumer electronics
• Wireless game controllers
Product Description
CC2500
The
is a low-cost 2.4 GHz transceiver
designed for very low-power wireless appli-
cations. The circuit is intended for the 2400-
2483.5 MHz ISM (Industrial, Scientific and
Medical) and SRD (Short Range Device)
frequency band.
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
supports various modulation formats and has
a configurable data rate up to 500 kBaud.
CC2500
provides extensive hardware support
for packet handling, data buffering, burst
transmissions, clear channel assessment, link
quality indication, and wake-on-radio.
The main operating parameters and the 64-
byte transmit/receive FIFOs of
Key Features
RF Performance
High sensitivity (–104 dBm at 2.4 kBaud,
1% packet error rate)
Low current consumption (13.3 mA in RX,
250 kBaud, input well above sensitivity
limit)
Programmable output power up to +1 dBm
Excellent receiver selectivity and blocking
performance
Programmable data rate from 1.2 to 500
kBaud
Frequency range: 2400 – 2483.5 MHz
Analog Features
OOK, 2-FSK, GFSK, and MSK supported
Suitable for frequency hopping and multi-
channel systems due to a fast settling
• Wireless audio
• Wireless keyboard and mouse
• RF enabled remote controls
controlled via an SPI interface. In a typical
system, the
a microcontroller and a few additional passive
components.
CC2500
can be
frequency synthesizer with 90 us settling
time
Automatic
(AFC) can be used to align the frequency
synthesizer
frequency
Integrated analog temperature sensor
Digital Features
Flexible
systems: On-chip support for sync word
detection, address check, flexible packet
length, and automatic CRC handling
Efficient SPI interface: All registers can be
programmed with one “burst” transfer
Digital RSSI output
Programmable channel filter bandwidth
Programmable
indicator
SWRS040B
CC2500
will be used together with
Frequency
Compensation
to
the
received
centre
support
for
packet
oriented
Carrier
Sense
(CS)
Page 1 of 92

CC2500 Summary of contents

  • Page 1

    ... CRC handling • Efficient SPI interface: All registers can be programmed with one “burst” transfer • Digital RSSI output • Programmable channel filter bandwidth • Programmable indicator SWRS040B CC2500 will be used together with Frequency Compensation to the received centre support for packet oriented ...

  • Page 2

    Programmable Preamble Quality Indicator (PQI) for improved protection against false sync word detection in random noise • Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) • Support for per-package Link Quality Indication (LQI) • Optional ...

  • Page 3

    Abbreviations Abbreviations used in this data sheet are described below. ACP Adjacent Channel Power ADC Analog to Digital Converter AFC Automatic Frequency Offset Compensation AGC Automatic Gain Control AMR Automatic Meter Reading ARIB Association of Radio Industries and Businesses BER ...

  • Page 4

    Table of Contents APPLICATIONS ...........................................................................................................................................1 PRODUCT DESCRIPTION.........................................................................................................................1 KEY FEATURES .......................................................................................................................................... ...........................................................................................................................................1 ERFORMANCE A F ..........................................................................................................................................1 NALOG EATURES D F ..........................................................................................................................................1 IGITAL EATURES ...................................................................................................................................2 OW OWER EATURES G ..........................................................................................................................................................2 ENERAL ABBREVIATIONS........................................................................................................................................3 TABLE OF CONTENTS ..............................................................................................................................4 1 ...

  • Page 5

    A M .................................................................................................................35 MPLITUDE ODULATION ECEIVED IGNAL UALIFIERS AND 17 .....................................................................................................................35 YNC ORD UALIFIER 17 REAMBLE UALITY HRESHOLD 17.3 RSSI...................................................................................................................................................35 17 (CS)..........................................................................................................................36 ARRIER ENSE 17 ...

  • Page 6

    A I .....................................................................................................................91 DDRESS NFORMATION ORLDWIDE ECHNICAL S ...............................................................................................91 UPPORT SWRS040B Page ...

  • Page 7

    ... Voltage on the pins RF_P, RF_N and DCOUPL Voltage ramp-up rate Input RF level Storage temperature range Solder reflow temperature ESD Table 1: Absolute Maximum Ratings 2 Operating Conditions CC2500 The operating conditions are listed in Table 2 below. Parameter Operating temperature Operating supply voltage 3 General Characteristics Parameter Min ...

  • Page 8

    ... Electrical Specifications 4.1 Current Consumption Tc = 25°C, VDD = 3 nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Min Current consumption in power down modes Current consumption Current consumption, RX states Typ Max Unit Condition 400 nA Voltage regulator to digital part off, register values retained (SLEEP state) ...

  • Page 9

    Current consumption, 11.1 TX states 15.0 21.2 21.5 mA Transmit mode, –12 dBm output power mA Transmit mode, -6 dBm output power mA Transmit mode, 0 dBm output power mA Transmit mode, +1 dBm output power Table 4: Current Consumption ...

  • Page 10

    ... RF Receive Section Tc = 25°C, VDD = 3 nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Min Typ Digital channel filter 58 bandwidth 2.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 203 kHz digital channel filter bandwidth) Receiver sensitivity – ...

  • Page 11

    Parameter Min 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection Blocking ±10 MHz offset ±20 MHz offset ...

  • Page 12

    ... RF Transmit Section Tc = 25°C, VDD = 3 dBm if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Min Typ Differential load 80 + j74 impedance Output power, +1 highest setting Output power, –30 lowest setting Occupied bandwidth 91 (99%) 117 296 489 ...

  • Page 13

    ... Tolerance ±40 ESR Start-up time 150 Table 7: Crystal Oscillator Parameters 4.5 Low Power RC Oscillator Tc = 25°C, VDD = 3 nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Min Calibrated frequency 34.7 Frequency accuracy after calibration Temperature coefficient Supply voltage coefficient ...

  • Page 14

    ... Frequency Synthesizer Characteristics Tc = 25°C, VDD = 3 nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal. Parameter Min Typ Programmed ...

  • Page 15

    Analog Temperature Sensor The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor ...

  • Page 16

    Pin Configuration SO (GDO1) DCOUPL Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip SCLK 1 15 AVDD 2 ...

  • Page 17

    ... V analog power supply connection Analog ground connection External bias resistor for reference current Power supply connection for digital noise isolation Ground connection for digital noise isolation Serial configuration interface, data input Table 13: Pinout Overview SWRS040B CC2500 only. It can not be Page ...

  • Page 18

    ... RADIO CONTROL ADC ADC FREQ SYNTH XOSC XOSC_Q1 XOSC_Q2 CC2500 Simplified Block Diagram signals to the down-conversion mixers in is shown receive mode. A crystal connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part. ...

  • Page 19

    ... Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to is highly achieve CC2500EM CC2500EM reference design ([4]) should be followed closely. R171 AVDD 15 AVDD 14 CC2500 RF_N 13 DIE ATTACH PAD: ...

  • Page 20

    ... Table 15: Bill Of Materials for the Application Circuit Measurements have been performed with multi-layer inductors from other manufacturers (e.g. Würth) and the measurement results were the same as when using the Murata part. The Gerber files for the CC2500EM reference design ([4]) are available from the TI website. 8 Configuration Overview CC2500 can be configured to achieve optimum performance for many different applications ...

  • Page 21

    ... Studio The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the CC2500 SPI interface. SWRS040B Lowest power mode. Most register values are retained. Typ. current consumption ...

  • Page 22

    ... The timing for the address and data transfer on the SPI interface is shown in Figure 7 with reference to Table 16. When CSn is pulled low, the MCU must wait CC2500 until SO pin goes low before starting to transfer the header byte. This indicates that – ...

  • Page 23

    ... CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator start-up time measured on CC2500EM reference design ([4]) using crystal AT-41CD2 from NDK. 10.1 Chip Status Byte ...

  • Page 24

    ... The number of bytes available in the RX FIFO or free bytes in the TX FIFO Table 17: Status Byte Summary burst bit (B) in the header byte. The address bits (A 5 CC2500 are internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high ...

  • Page 25

    ... CC2500 the Errata Notes [1] for more details. 10.4 Command Strobes Command strobes may be viewed as single CC2500 byte instructions addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 13 command strobes are listed in Table 34 on page 58 ...

  • Page 26

    ... See Section 24 on page 47 for output power programming details. Figure 9: Register Access Types 11.2 General Control and Status Pins CC2500 The pins (GDO0 and GDO2) and one shared pin (GDO1) that information useful for control software. These pins can be used to generate interrupts on the MCU ...

  • Page 27

    ... IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value (0x7F). 11.3 Optional Radio Control Feature CC2500 The has an optional way of controlling the radio, by reusing SI, SCLK and CSn from the SPI interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE, RX and TX ...

  • Page 28

    ... GHz, which is ±98 kHz. If the whole transmitted signal oscillator bandwidth received within 480 kHz, the transmitted signal bandwidth should be maximum 480 kHz – 2·98 kHz, which is 284 kHz. CC2500 The filter bandwidths: CHANBW )· 2 MDMCFG4 ...

  • Page 29

    ... CRC_OK 6:0 LQI Table 22: Received Packet Status Byte 2 (second byte appended after the data) Note that register fields that control the packet packet by handling features should only be altered when CC2500 is in the IDLE state. SWRS040B likely, a mechanism called Description RSSI value Description ...

  • Page 30

    ... Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening the data in the CC2500 receiver. With , this can be done 15.2 Packet Format The format of the data packet can be ...

  • Page 31

    ... TXOFF_MODE CRC appending/checking can also be used (by setting PKTCTRL0.CRC_EN=1). When for example a 600-byte packet transmitted, the MCU should do the following (see also Figure 12): • Set PKTCTRL0.LENGTH_CONFIG=2. SWRS040B CC2500 Errata Notes [1] for more the minimum packet must enters the state determined or RXOFF_MODE) ...

  • Page 32

    ... Infinite packet length enabled Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256 15.3 Packet Filtering in Receive Mode CC2500 supports three different types of packet-filtering: address filtering, maximum length filtering and CRC filtering. 15.3.1 Address Filtering Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter ...

  • Page 33

    ... CC2500 options. Refer also to the [1]. 15.4.1 PKTCTRL0.CC2400_EN=0 If PKTCTRL0.CC2400_EN possible to read back the CRC status in 2 different ways: 1) Set PKTCTRL1.APPEND_STATUS=1 and read the CRC_OK flag in the MSB of the second byte appended to the RX FIFO after the packet data. This requires double buffering of the packet, i.e. the entire packet content of ...

  • Page 34

    ... Phase shifts are performed with a constant transition time. 1 Identical to offset QPSK with half-sine shaping (data coding may differ) SWRS040B ⋅ + ⋅ DEVIATION xosc 8 ( DEVIATION Symbol Coding ‘0’ – Deviation ‘1’ + Deviation Modulation Minimum Shift Keying 1 , the complete transmission Page CC2500 _ E ...

  • Page 35

    ... Sync Word Qualifier If sync word detection enabled in CC2500 register MDMCFG2 the filling the RX FIFO and perform the packet filtering described in Section 15.3 before a valid sync word has been detected. The sync word ...

  • Page 36

    The RSSI value read from the RSSI status register is a 2’s complement number. The following procedure can be used to convert the RSSI reading to an absolute power ...

  • Page 37

    IOCFGx.GDOx_CFG=14 and in the status register bit PKTSTATUS.CS. Other uses of Carrier Sense include the TX-if- CCA function (see Section 17.5 on page 38) and the optional fast RX termination (see Section 19.7 on page 44). CS can be used ...

  • Page 38

    ... FEC necessary to use twice as high over-the-air data rate. This will require a higher receiver sensitivity. In other words, the improved _ length reception by using FEC and the degraded sensitivity from a higher receiver bandwidth will be counteracting factors. SWRS040B CC2500 bandwidth, and thus reduce Page ...

  • Page 39

    ... In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart. CC2500 employs matrix interleaving, which is illustrated in Figure 14. interleaving and de-interleaving buffers are matrices. In the transmitter, the data bits from the rate ½ ...

  • Page 40

    ... FS_ AUTOCAL = TXFIFO_UNDERFLOW 22 SFTX Figure 15: Complete Radio Control State Diagram CC2500 has a built-in state machine that is used to switch between different operation states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow. A simplified state diagram, together with typical usage and current consumption, is shown in Figure 5 on page 16 ...

  • Page 41

    ... IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state CC2500 machine will then go to the IDLE state. The SO is pin on the SPI interface must be pulled low before the SPI interface is ready to be used ...

  • Page 42

    ... Event 1. In the SLEEP state with WOR activated, reaching Event 0 will turn on the digital regulator and start the crystal oscillator. SWRS040B as indicated by the setting controls the on Radio (WOR) CC2500 to periodically CC2500 will go to the is received, the will determine the Page ...

  • Page 43

    ... Refer to Application Note AN047 [3] for further details. 19.6 The radio controller controls most timing in CC2500 lock time and RX/TX turnaround times. Timing from IDLE to RX and IDLE constant, dependent on the auto calibration setting. RX/TX and TX/RX turnaround times are constant. The calibration time is constant 18739 clock periods ...

  • Page 44

    ... See Section 17.4 on page 36 for details on Carrier Sense. 20 Data FIFO CC2500 The contains two 64 byte FIFOs, one for received data and one for data to be transmitted. The SPI interface is used to read from the RX FIFO and write to the TX FIFO ...

  • Page 45

    ... Figure 20: Example of FIFOs at Threshold CC2500 is MDMCFG1.CHANSPC_E registers. The channel programming spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1 and and FREQ0 registers. This word will typically ...

  • Page 46

    ... PLL lock is achieved if the PLL time the does not lock the first time. mode, the the SCAL SWRS040B ) ) ) ⋅ − CHANSPC ® Studio software [5] calculates the optimum the synthesizer may give CC2500 Errata Notes Page ...

  • Page 47

    ... PATABLE(0) (OOK modulation). Note that all content of the PATABLE, except for the first byte (index 0) is lost when entering the SLEEP state. and The 3-bit SWRS040B CC2500 . for various output levels ® Studio software [5] should be used Page ...

  • Page 48

    Figure 21: PA_POWER and PATABLE Default power setting 0xC6 Table 30: Output Power and Current Consumption for Default PATABLE Setting Output power, typical, +25°C, 3.0 V [dBm] (–55 or less) –30 –28 –26 –24 –22 –20 –18 –16 –14 –12 ...

  • Page 49

    Selectivity Figure 22 to Figure 26 show the typical selectivity performance (adjacent and alternate rejection). -1 -0.8 Figure 22: Typical Selectivity at 2.4 kBaud. IF Frequency is 273.9 kHz. -1 -0.8 Figure 23: Typical Selectivity at 10 kBaud. IF ...

  • Page 50

    Figure 24: Typical Selectivity at 250 kBaud. IF Frequency is 177.7 kHz. MDMCFG2.DEM_DCFILT_OFF Figure 25: Typical Selectivity at 250 kBaud. IF Frequency is 457 kHz. MDMCFG2.DEM_DCFILT_OFF Figure 26: Typical Selectivity at ...

  • Page 51

    ... RF- port (RF_P and RF_N) towards the antenna: SWRS040B are given in Table 32. L XOSC_Q1 XOSC_Q2 XTAL C81 C101 C = using a XOSC_Q1 CC2500 has a balanced passive matching/filtering CC2500 should have the following Page serial RF network ...

  • Page 52

    ... Each decoupling capacitor should be connected to the power Figure 28: Left: Top Solder Resist Mask (negative). Right: Top Paste Mask. Circles are Vias. follow the CC2500EM reference designs [4] as closely as possible. Gerber files for the CC2500 reference designs are available for download from the TI website ...

  • Page 53

    General Purpose / Test Output Control Pins The three digital output pins GDO0, GDO1 and GDO2 are general control pins configured with IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG respectively. Table 33 shows the different signals that can be monitored on the ...

  • Page 54

    ... The GDO0 default value is CLK_XOSC/192. 56 (0x38) CLK_XOSC/16 57 (0x39) CLK_XOSC/24 58 (0x3A) CLK_XOSC/32 59 (0x3B) CLK_XOSC/48 60 (0x3C) CLK_XOSC/64 61 (0x3D) CLK_XOSC/96 62 (0x3E) CLK_XOSC/128 63 (0x3F) CLK_XOSC/192 Table 33: GDOx Signal Selection ( CC2500 when GDOx_INV =0. CC2500 on the rising edge of the serial clock when SWRS040B GDOx_INV =0. Page ...

  • Page 55

    ... Application Note AN032 [2]. Please note that compliance with regulations is dependent performance the customer’s responsibility to ensure that the system complies with regulations. SWRS040B Synchronous Serial Operation PKTCTRL0.PKT_FORMAT CC2500 sync word insertion CC2500 This is equivalent to on complete ...

  • Page 56

    ... SWRS040B each frequency hop is more memory space to values. Solution 3) Wideband Modulation not Using Spread Spectrum CC2500 is suited for Data Burst Transmissions CC2500 Continuous Transmissions CC2500 loop modulation used in Page then store gives opens some ...

  • Page 57

    ... T/R switch Figure 29. Block Diagram of 3. The CC25XX Folded Dipole reference design [8] contains schematics and layout files for a CC2500EM with a folded dipole PCB antenna. Please see DN004 [9] for more details on this design. A HC-49 type SMD crystal is used in the CC2500EM reference design [4]. Note that the crystal package strongly influences the price ...

  • Page 58

    ... Table 37 summarizes the SPI address space. The address to use is given by adding the base address to the left and the burst and R/W bits on the top. Note that the burst bit has different meaning for base addresses above and below 0x2F. CC2500 . Table 34: Command Strobes SWRS040B Page ...

  • Page 59

    Address Register Description GDO2 output pin configuration 0x00 IOCFG2 0x01 IOCFG1 GDO1 output pin configuration GDO0 output pin configuration 0x02 IOCFG0 0x03 FIFOTHR RX FIFO and TX FIFO thresholds 0x04 SYNC1 Sync word, high byte 0x05 SYNC0 Sync word, low ...

  • Page 60

    ... RXBYTES 0x3C (0xFC) RCCTRL1_STATUS 0x3D (0xFD) RCCTRL0_STATUS Table 36: Status Registers Overview Description CC2500 part number Current version number Frequency offset estimate Demodulator estimate for Link Quality Received signal strength indication Control state machine state High byte of WOR timer Low byte of WOR timer ...

  • Page 61

    Write Single byte Burst +0x00 +0x40 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRL0 0x09 ADDR 0x0A CHANNR 0x0B FSCTRL1 0x0C FSCTRL0 0x0D FREQ2 0x0E FREQ1 0x0F FREQ0 0x10 MDMCFG4 ...

  • Page 62

    Configuration Register Details – Registers with Preserved Values in SLEEP State 0x00: IOCFG2 – GDO2 Output Pin Configuration Bit Field Name 7 Reserved 6 GDO2_INV 5:0 GDO2_CFG[5:0] 0x01: IOCFG1 – GDO1 Output Pin Configuration Bit Field Name 7 GDO_DS ...

  • Page 63

    FIFOTHR – RX FIFO and TX FIFO Thresholds Bit Field Name 7:4 Reserved 3:0 FIFO_THR[3:0] 0x04: SYNC1 – Sync Word, High Byte Bit Field Name 7:0 SYNC[15:8] 0x05: SYNC0 – Sync Word, Low Byte Bit Field Name 7:0 SYNC[7:0] ...

  • Page 64

    PKTCTRL1 – Packet Automation Control Bit Field Name Reset 7:5 PQT[2:0] 0 (000) 4 Reserved 0 3 CRC_AUTOFLUSH 0 2 APPEND_STATUS 1 1:0 ADR_CHK[1:0] 0 (00) R/W Description R/W Preamble quality estimator threshold. The preamble quality estimator increases an ...

  • Page 65

    PKTCTRL0 – Packet Automation Control Bit Field Name 7 Reserved 6 WHITE_DATA 5:4 PKT_FORMAT[1:0] 3 CC2400_EN 2 CRC_EN 1:0 LENGTH_CONFIG[1:0] Bit Field Name 7:0 DEVICE_ADDR[7:0] 0x0A: CHANNR – Channel Number Bit Field Name Reset 7:0 CHAN[7:0] 0 (0x00) Reset ...

  • Page 66

    FSCTRL1 – Frequency Synthesizer Control Bit Field Name Reset 7:5 Reserved 4:0 FREQ_IF[4:0] 15 (0x0F) 0x0C: FSCTRL0 – Frequency Synthesizer Control Bit Field Name 7:0 FREQOFF[7:0] 0x0D: FREQ2 – Frequency Control Word, High Byte Bit Field Name Reset 7:6 ...

  • Page 67

    MDMCFG4 – Modem Configuration Bit Field Name Reset 7:6 CHANBW_E[1:0] 2 (10) 5:4 CHANBW_M[1:0] 0 (00) 3:0 DRATE_E[3:0] 12 (1100) 0x11: MDMCFG3 – Modem Configuration Bit Field Name Reset 7:0 DRATE_M[7:0] 34 (0x22) R/W Description R/W R/W Sets the ...

  • Page 68

    MDMCFG2 – Modem Configuration Bit Field Name 7 DEM_DCFILT_OFF 6:4 MOD_FORMAT[2:0] 3 MANCHESTER_EN 2:0 SYNC_MODE[2:0] Reset R/W Description 0 R/W Disable digital DC blocking filter before demodulator Enable (better sensitivity Disable (current optimized). Only for ...

  • Page 69

    MDMCFG1 – Modem Configuration Bit Field Name Reset 7 FEC_EN 0 6:4 NUM_PREAMBLE[2:0] 2 (010) 3:2 Reserved 1:0 CHANSPC_E[1:0] 2 (10) 0x14: MDMCFG0 – Modem Configuration Bit Field Name Reset 7:0 CHANSPC_M[7:0] 248 (0xF8) R/W Description R/W Enable Forward ...

  • Page 70

    DEVIATN – Modem Deviation Setting Bit Field Name Reset 7 Reserved 6:4 DEVIATION_E[2:0] 4 (100) 3 Reserved 2:0 DEVIATION_M[2:0] 7 (111) R/W Description R0 R/W Deviation exponent R0 R/W When MSK modulation is enabled: Sets fraction of symbol period ...

  • Page 71

    MCSM2 – Main Radio Control State Machine Configuration Bit Field Name 7:5 Reserved 4 RX_TIME_RSSI 3 RX_TIME_QUAL 2:0 RX_TIME[2:0] The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and ...

  • Page 72

    MCSM1 – Main Radio Control State Machine Configuration Bit Field Name 7:6 Reserved 5:4 CCA_MODE[1:0] 3:2 RXOFF_MODE[1:0] 1:0 TXOFF_MODE[1:0] Reset R/W Description R0 3 (11) R/W Selects CCA_MODE; Reflected in CCA signal Setting Clear channel indication 0 (00) Always ...

  • Page 73

    MCSM0 – Main Radio Control State Machine Configuration Bit Field Name Reset 7:6 Reserved 5:4 FS_AUTOCAL[1:0] 0 (00) 3:2 PO_TIMEOUT 1 (01) 1 PIN_CTRL_EN 0 0 XOSC_FORCE_ON 0 R/W Description R0 R/W Automatically calibrate when going ...

  • Page 74

    FOCCFG – Frequency Offset Compensation Configuration Bit Field Name 7:6 Reserved 5 FOC_BS_CS_GATE 4:3 FOC_PRE_K[1:0] 2 FOC_POST_K 1:0 FOC_LIMIT[1:0] Reset R/W Description R0 1 R/W If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops ...

  • Page 75

    BSCFG – Bit Synchronization Configuration Bit Field Name Reset 7:6 BS_PRE_KI[1:0] 1 (01) 5:4 BS_PRE_KP[1:0] 2 (10) 3 BS_POST_KI 1 2 BS_POST_KP 1 1:0 BS_LIMIT[1:0] 0 (00) R/W Description R/W The clock recovery feedback loop integral gain to be ...

  • Page 76

    Bit Field Name Reset 7:6 MAX_DVGA_GAIN[1:0] 0 (00) 5:3 MAX_LNA_GAIN[2:0] 0 (000) 2:0 MAGN_TARGET[2:0] 3 (011) 0x1B: AGCCTRL2 – AGC Control R/W Description R/W Reduces the maximum allowable DVGA gain. Setting Allowable DVGA settings 0 (00) All gain settings can ...

  • Page 77

    Bit Field Name 7 Reserved 6 AGC_LNA_PRIORITY 5:4 CARRIER_SENSE_REL_THR[1:0] 3:0 CARRIER_SENSE_ABS_THR[3:0] 0x1C: AGCCTRL1 – AGC Control Reset R/W Description R0 1 R/W Selects between two different strategies for LNA and LNA2 gain adjustment. When 1, the LNA gain is decreased ...

  • Page 78

    Bit Field Name 7:6 HYST_LEVEL[1:0] 5:4 WAIT_TIME[1:0] 3:2 AGC_FREEZE[1:0] 1:0 FILTER_LENGTH[1:0] 0x1E: WOREVT1 – High Byte Event0 Timeout Bit Field Name Reset 7:0 EVENT0[15:8] 135 (0x87) 0x1D: AGCCTRL0 – AGC Control Reset R/W Description 2 (10) R/W Sets the level ...

  • Page 79

    WOREVT0 – Low Byte Event0 Timeout Bit Field Name Reset 7:0 EVENT0[7:0] 107 (0x6B) 0x20: WORCTRL – Wake On Radio Control Bit Field Name Reset 7 RC_PD 1 6:4 EVENT1[2:0] 7 (111) 3 RC_CAL 1 2 Reserved 1:0 WOR_RES[1:0] ...

  • Page 80

    FREND0 – Front End TX configuration Bit Field Name 7:6 Reserved 5:4 LODIV_BUF_CURRENT_TX[1:0] 3 Reserved 2:0 PA_POWER[2:0] 0x23: FSCAL3 – Frequency Synthesizer Calibration Bit Field Name 7:6 FSCAL3[7:6] 5:4 CHP_CURR_CAL_EN[1:0] 3:0 FSCAL3[3:0] 0x24: FSCAL2 – Frequency Synthesizer Calibration Bit ...

  • Page 81

    FSCAL1 – Frequency Synthesizer Calibration Bit Field Name 7:6 Reserved 5:0 FSCAL1[5:0] 0x26: FSCAL0 – Frequency Synthesizer Calibration Bit Field Name 7 Reserved 6:0 FSCAL0[6:0] 0x27: RCCTRL1 – RC Oscillator Configuration Bit Field Name 7 Reserved 6:0 RCCTRL1[6:0] 0x28: ...

  • Page 82

    Bit Field Name Reset 7:0 AGCTEST[7:0] 63 (0x3F) 0x2C: TEST2 – Various Test Settings Bit Field Name Reset 7:0 TEST2[7:0] 136 (0x88) 0x2D: TEST1 – Various Test Settings Bit Field Name Reset 7:0 TEST1[7:0] 49 (0x31) 0x2E: TEST0 – Various ...

  • Page 83

    LQI – Demodulator Estimate for Link Quality Bit Field Name Reset 7 CRC_OK 6:0 LQI_EST[6:0] 0x34 (0xF4): RSSI – Received Signal Strength Indication Bit Field Name Reset 7:0 RSSI 0x35 (0xF5): MARCSTATE – Main Radio Control State Machine ...

  • Page 84

    WORTIME1 – High Byte of WOR Time Bit Field Name Reset 7:0 TIME[15:8] 0x37 (0xF7): WORTIME0 – Low Byte of WOR Time Bit Field Name Reset 7:0 TIME[7:0] 0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status ...

  • Page 85

    RXBYTES – Underflow and Number of Bytes Bit Field Name Reset 7 RXFIFO_OVERFLOW 6:0 NUM_RXBYTES 0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result Bit Field Name Reset 7 Reserved 6:0 RCCTRL1_STATUS[6:0] 0x3D (0xFC): RCCTRL0_STATUS – Last RC ...

  • Page 86

    ... All dimensions are in millimetres, angles in degrees. NOTE: The lead-free package only. Figure 30: Package Dimensions Drawing Package type A A1 Min 0.75 0.005 QLP 20 (4x4) Typ. 0.85 0.025 Max 0.95 0.045 0.55 3.90 3.65 3.90 0.65 4.00 3.75 2.40 4.00 0.75 4.10 3.85 4.10 Table 38: Package Dimensions SWRS040B CC2500 is available in RoHS 3.65 0.45 0.190 0.18 3.75 2.40 0.55 0.23 3.85 0.65 0.245 0.30 Page 0.50 ...

  • Page 87

    ... Figure 31: Recommended PCB Layout for QLP 20 Package Note: The figure is an illustration only and not to scale. There are five 10 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC2500EM reference design [4]. Table 39: Thermal Properties for QPL 20 Package 33 ...

  • Page 88

    ... AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf) [4] CC2500EM Reference Design 1.0 (swrr016.zip) ® [5] SmartRF Studio (swrc046.zip) [6] CC1100 CC2500 Examples Libraries (swrc021.zip) [7] CC1100/CC1150DK & CC2500/CC2550DK Development Kit Examples & Libraries User Manual (swru109.pdf) [8] CC25XX Folded Dipole Reference Design (swrc065.zip) [9] DN004 Folded Dipole Antenna for CCC25xx (swra118.pdf) Component Hole ...

  • Page 89

    General Information 36.1 Document History Revision Date Description/Changes SWRS040B 2007-05-09 kbps replaced by kBaud throughout the document. Some of the sections have been re-written to be easier to read without having any new info added. Absolute maximum supply voltage ...

  • Page 90

    Revision Date Description/Changes 2006-06-28 Added figures to table on SPI interface timing requirements. 1.2 Added information about SPI read. SWRS040A Updates to text and included new figure in section on arbitrary length configuration. Updates to section on CRC check. Added ...

  • Page 91

    Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: + Fax: + Web site: http://www.ti.com/lpw 38 TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page: ...

  • Page 92

    Asia International Phone Domestic Australia China Hong Kong India Indonesia Korea Malaysia New Zealand Philippines Singapore Taiwan Thailand Fax Email Internet +886-2-23786800 Toll-Free Number 1-800-999-084 800-820-8682 800-96-5941 +91-80-51381665 (Toll) 001-803-8861-1006 080-551-2804 1-800-80-3973 0800-446-934 1-800-765-7404 800-886-1028 0800-006800 001-800-886-0010 +886-2-2378-6808 tiasia@ti.com or ...

  • Page 93

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...