STE10-100A STMicroelectronics, STE10-100A Datasheet
STE10-100A
Related parts for STE10-100A
STE10-100A Summary of contents
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... QFP package February 2007 STE10/100A PQFP128 (14mm x 20mm x 2.7mm) Description The STE10/100A is a high performing PCI fast ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide glueless 32-bit bus master interface for ...
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... LED display operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7 Reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7.1 3.7.2 3.8 Wake on LAN function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.9 ACPI power management function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.9.1 4 Registers and descriptors description . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 STE10/100A configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.1 4.2 PCI control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 Transceiver(XCVR) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2/82 Descriptor structure types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Descriptor management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transmit scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transmit pre-fetch data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transmit early interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transceiver operation ...
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... STE10/100A 4.4 Descriptors and buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.1 4.4.2 5 General EEPROM format description . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6 Electrical specifications and timings . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.1 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Receive descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Contents 3/82 ...
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... Overview 1 Overview 1.1 Block diagrams Figure 1. STE10/100A block diagram Flow control EMI Figure 2. STE10/100A system diagram PCI interface 4/82 Manchester encoder 4B/5B DMA Auto-negociation Tx FiFo 5B/4B Rx FiFo 100 clock recovery Serial EEPROM Boot ROM STE10/100A LEDs 25MHz crystal STE10/100A 10 TX filter Scrambler Transmitter 25MHz TX freq. synth. ...
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... STE10/100A 1.2 Detailed features FIFO ● Provides independent transmission and receiving FIFOs, each 2k bytes long ● Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us ● Retransmits collided packet without reload from host memory within 64 bytes. ● Automatically retransmits FIFO under-run packet with maximum drain threshold until 3rd time retry failure threshold of next packet ...
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... Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in full duplex mode) or when collision detected (Blinks at 20Hz) ● LED is used, then: Pull the pins 90, 91 high with 4.7K resistor (see STE10/100A evaluation board schematics for details) 6/82 STE10/100A ...
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... STE10/100A 2 Pin description Figure 3. Pin connection Pin description 7/82 ...
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... I STE10/100A completes initialization. During the reset period, all the output pins of STE10/100A will be placed in a high- impedance state and all the O/D pins are floated. PCI clock input to STE10/100A for PCI bus functions. The ...
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... BrWE# Type I/O Bus command and byte enable Initialization device select. This signal is asserted when the I host issues configuration cycles to the STE10/100A. I/O Asserted by PCI bus master during bus tenure I/O Master device is ready to begin data transaction I/O Target device is ready to begin data transaction Device select. Indicates that a PCI target device address has ...
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... For mode 1: LED display for 100M b/s or 10M b/s speed. This pin will be driven on continually when the 100M b/s network operating O speed is detected. For mode 2: LED display for 100Ms/s link status. This pin will be driven on continually when 100Mb/s network operating speed is detected. STE10/100A Description ...
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... STE10/100A Table 1. Pin description (continued) Pin no. Name LED M1- Fd/Col 91 or LED M2- 10 link 89 Vaux-detect 88 Vcc-detect Digital power pins 5,11,19,31,36,39,45,51,55,75,93,112,115,125 8,14,27,38,40,48,60,85,111,122,128 Analog power pins 94,96,102,106,110 95,99,100,103,108 Type This pin can be programmed as mode 1 or mode 2: For mode 1: LED display for full duplex or collision status. This pin will be driven on continually when a full duplex configuration is detected ...
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... Functional description 3 Functional description 3.1 Initialization flow Figure 4. STE10/100A initialization flow Search NIC Get base IO address Get IRQ value Reset MAC (CSR0) Reset PHY (XR0) Read EEPROM from CSR9 Set physical address (CSR25, 26) Prepare transmit descriptor and buffer Prepare receive descriptor and buffer ...
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... There are two types of structures employed to group descriptors, the Ring and the Chain, both supported by the STE10/100A and shown below. The selection of structure type is controlled by RCH (RDES1 bit 24) and TCH (TDES1 bit 24). The transmit and receive buffers reside in the host’s memory. Any buffer can contain either a complete or partial packet ...
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... There is only one buffer per descriptor in chain structure. Figure 6. Frame buffer chain structure CSR3 or CSR4 Descriptor pointer 14/82 Descriptor own --- Length 1 Data buffer Buffer1 pointer Next pointer own --- Length 2 Buffer1 pointer Next pointer own --- Length 3 Buffer1 pointer Next pointer . . . STE10/100A Length 1 Data Data Length 2 Length 3 Data . . . PC00351 ...
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... STE10/100A 3.2.2 Descriptor management OWN bit = 1, ready for network side access OWN bit = 0, ready for host side access Transmit descriptors Figure 7. Transmit descriptor management Ext packet to be transmitted Ext packet to be transmitted Own bit=1, Own bit=1, packet 1 and packet 2 packet 1 and packet 2 ...
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... Next descriptor ready for incoming packet for incoming packet Filled descriptor pointer Filled descriptor pointer 16/ Packet 2 Packet Packet 1 Packet 1 • • • • • • End of ring End of ring Packet 2 Packet 2 STE10/100A Data Data buffer buffer PC00353 ...
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... Place data in host memory Place data in host memory Set own bit to 1 Set own bit to 1 Write Tx demand poll command Write Tx demand poll command STE10/100 STE10/100 checks descriptor checks descriptor Own = 1 Own = 1 Transfer data to Tx FIFO Transfer data to Tx FIFO Deferring OR data less ...
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... STE10/100A IFG 2nd packet Check the next packet 1st packet is transmitted, check the 3rd packet : handled by STE10/100A The saved time when transmit The saved time when transmit early interrupt is implemented early interrupt is implemented : handled by STE10/100A : handled by STE10/100A PC00355 PC00356 ...
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... STE10/100A 3.4 Receive scheme and receive early interrupt scheme The following figure shows the difference of timing without early interrupt and with early interrupt. Figure 12. Receive data flow (without early interrupt and with early interrupt) Incoming packet Receive FIFO operation FIFO-to-host memory operation ...
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... Receive data decapsulation When operating in 100BASE-TX mode the STE10/100A detects a JK code in a preamble as well code at the packet end code is not detected, the STE10/100A will abort the reception of the frame and wait for a new JK code detection code is not detected, the STE10/100A will report a CRC error ...
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... The scheduling of re-transmissions are determined by a controlled randomization process called “truncated binary exponential back-off”. At the end of enforcing a collision (jamming), the STE10/100A delays before attempting to re-transmit the packet. The delay is an integer multiple of slot time. The number of slot times to delay before the nth re-transmission ...
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... MLT3 to NRZI decoder and PLL for data recovery Following adaptive equalizer, baseline wander, the transceiver converts the resulting MLT3 to NRZI code, which is passed to the Phase Lock Loop circuits in order to extract the synchronous clock and the original data. 22/82 STE10/100A ...
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... STE10/100A Data conversions of NRZI to NRZ and serial to parallel After the data is recovered, it will be passed to the NRZI-to-NRZ converter to produce a 125MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion may be bypassed by clearing ENRZI (bit 7 of XR10 ...
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... Power down operation The transceiver is designed with a power-down feature which can reduce power consumption significantly. Since the power supply of the 100BASE-TX and 10BASE-T circuits are separate, the transceiver can turn off the circuit of either the 100BASE-TX or 10BASE-T when the other is active. 24/82 STE10/100A ...
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... Flow control in full duplex application The PAUSE function is used to inhibit transmission of data frames for a specified period of time. The STE10/100A supports the full duplex protocol of IEEE802.3x. To support the PAUSE function, the STE10/100A implements the MAC Control Sub-layer functions to decode the MAC Control frames received from MAC control clients and to execute the relative requests accordingly ...
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... MAC is begun, it can’t be interrupted). Conversely, the STE10/100A will not begin to transmit a frame more than one slot-time after valid PAUSE frame is received a with a non-zero PAUSE time. If the STE10/100A receives a PAUSE frame with a zero PAUSE time value, the STE10/100A exits the PAUSE state immediately. ...
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... Software reset Via SWR (bit 0 of CSR0) being set to 1 (the STE10/100A will reset all circuits except the transceivers and configuration registers, set registers to their default values, and will clear SWR) and set XRST(XR0, bit 15) to reset the transceivers. ...
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... Functional description 3.8 Wake on LAN function The STE10/100A can assert a signal to wake up the system when it has received a Magic Packet from the network. The wake on LAN operation is described as follow. The Magic Packet format – Valid destination address that can pass the address filter of the STE10/100A – ...
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... STE10/100A D3 (Software visible D3) hot When the STE10/100A is brought back to D0 from D3hot the software must perform a full initialization. The STE10/100A in the D3hot state responds to configuration cycles as long as power and clock are supplied. This requires the device to perform an internal reset and return to a power-up reset condition without the RST# pin asserted ...
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... STE10/100A and for identifying and querying the STE10/100A. The PCI control/status registers are used to communicate between the host and STE10/100A. The host can initialize, control, and read the status of the STE10/100A through mapped I/O or memory address space. The STE10/100A contains 11 16-bit registers to supported transceiver control and status. ...
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... STE10/100A Table 5. STE10/100A configuration registers table offset b31 00h 04h Base class 08h 0ch 10h 14h 18h~28h 2ch 30h 34h 38h 3ch Max_Lat 40h Reserved 80h c0h c4h 1. Automatically recalled from EEPROM when PCI reset is deserted DS(40h), bit15-8, is read/write able register ...
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... STE10/100A asserted parity error (PERR detected parity error asserted by another device. b. STE10/100A is operating as a bus master. c. STE10/100A’s parity error response bit (bit 6 of CR1) is enabled. Status fast back-to-back. Always 1, since STE10/100A has the ability to accept fast back to back transactions ...
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... Command I/O space access. 0: enable the I/O space access ability. 1: disable the I/O space access ability. Base class code. It means STE10/100A is a network controller. Subclass code. It means STE10/100A is a fast ethernet controller. Reserved ...
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... Cache line size. This value specifies the system cache line size in units of 32-bit double words (DW). The STE10/100A supports cache line sizes DW. CLS is used by the STE10/100A driver to program the cache alignment bits (bit 14 and 15 of CSR0) which are used for cache oriented PCI ...
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... ROM. (If bit 1 of CR1 is also set). Reserved Capabilities pointer Max_Lat register. This value indicates how often the STE10/100A needs to access to the PCI bus in units of 250ns. This value is loaded from serial EEPROM as a result of power-on or hardware reset. Min_Gnt register. This value indicates how long the STE10/100A needs to retain the PCI bus ownership whenever it initiates a transaction, in units of 250ns ...
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... PMEC 18~16 VER 15~8 NIP 36/82 Description Device ID, the device ID number of the STE10/100A Vendor ID, the vendor ID number of STMicroelectronics PME_Support. The STE10/100A will assert PME# signal while in the D0, D1, D2, D3hot and D3cold power state. The STE10/100A supports Wake-up from the above five states. Bit 31 (support wake-up from D3cold) is loaded from EEPROM after power-up or hardware reset ...
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... This field is required for any function that implements the data register. The STE10/100A does not support data register and Data_Scale. Data_Select. This four bit field is used to select which data reported through the data register and Data_Scale field ...
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... R/W1C: Read only and write one cleared 38/82 Description Reserved PowerState. This two bit field is used both to determine the current power state of the STE10/100A and to place the STE10/100A in a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot ...
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... STE10/100A 4.2 PCI control/status registers Table 7. PCI control/status registers list Offset from base address of CSR 00h 08h 10h 18h 20h 28h 30h 38h 40h 48h 50h 58h 60h 68h 70h 78h 80h 84h 88h 8ch 90h 94h 98h 9ch a0h a4h a8h ...
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... STE10/100A uses the memory read command instead. Reserved Memory read multiple enable. 1: enable STE10/100A to generate memory read multiple commands when reading a full cache line. If the memory is not cache-aligned, the STE10/100A uses the memory read command instead. ...
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... Software reset 1: Reset all internal hardware (excluding transceivers and configuration registers). This signal will be cleared by the STE10/100A itself after the reset process is completed. Transmit poll demand. While the STE10/100A is in the suspended state, a write to this register (any value) will trigger the read-tx-descriptor process, which checks the own-bit ...
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... FIFO drain, move data from receiving FIFO into memory Normal interrupt status summary. Set if any of the following bits of CSR5 are asserted: – TCI, transmit completed interrupt (bit 0) – TDU, transmit descriptor unavailable (bit 2) – RCI, receive completed interrupt (bit 6) STE10/100A Default RW type 000 RO 000 RO 000 RO 0 RO/LH* ...
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... STE10/100A. The receive process is suspended in this situation. To restart the receive process, the ownership bit of the next receive descriptor should be set to STE10/100A and a receive poll demand command should be issued (if the receive poll demand is not issued, the receive process will resume when a new recognized frame is received) ...
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... Store and forward for transmit 0: disable 1: enable, ignore the transmit threshold setting Reserved SQE disable 0: enable SQE function for 10BASE-T operation. The STE10/100A provides SQE test function for 10BASE-T half duplex operation. 1: disable SQE function. Reserved Transmit threshold control 00: 128-bytes (100Mbps), 72-bytes (10Mbps) ...
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... STE10/100A Table 8. Control/status register description (continued) Bit # Name --- SBC 4 --- --- --- W* = only write when the transmit processor stopped. W** = only write when the transmit and receive processor both stopped. W*** = only write when the receive processor stopped. ...
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... AIE (bit 15 of CSR7) will enable the transmit under-flow interrupt. Reserved Transmit jabber timer time-out interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the transmit jabber timer time- out interrupt. STE10/100A Default RW type 0 R/W 0 R/W 0 ...
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... When set, enables access to the serial EEPROM (see description of CSR9 bit 14 and CSR9 bit 13). Reserved Serial EEPROM data out. This bit serially shifts data from the EEPROM to the STE10/100A. Serial EEPROM data in. This bit serially shifts data from the STE10/100A to the EEPROM. Default RW type 0 R/W 0 R/W ...
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... OFF to ON. Reserved Wake-up frame received enable. The STE10/100A will include the “Wake-up Frame Received” event in its set of wake-up events. If this bit is set, STE10/100A will assert PMEST bit of PMR1 (CR49) after STE10/100A has received a matched wake-up frame. STE10/100A Default ...
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... STE10/100A has received a Magic packet. Link status changed enable. The STE10/100A will include the “Link status changed” event in its set of wake-up events. If this bit is set, STE10/100A will assert PMEST bit of PMR1 after STE10/100A has detected a link status changed event. Reserved Wake-up frame received, 1: Indicates STE10/100A has received a wake- up frame ...
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... Receive watchdog disable 0: If the received packet‘s length exceeds 2560 bytes, the watchdog timer will expire. 1: disable the receive watchdog. Reserved STE10/100A Default RW type Wake-up Reserved pattern 2 offset Wake-up Reserved ...
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... STE10/100A Table 8. Control/status register description (continued) Bit # Name 2 JCLK JBD CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2) 31 TEIS 30 REIS 29 XIS 28 TDIS 27 --- 26 PFR 25~ 23 BET Registers and descriptors description Description Jabber clock 0: cut off transmission after 2.6 ms (100Mbps (10Mbps). ...
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... These bits are the same as the status register of CSR5, and are accessible through either CSR5 or CSR16. Transmit early interrupt enable Receive early interrupt enable Transceiver (XCVR) interrupt enable Transmit deferred interrupt enable Reserved PAUSE frame received interrupt enable Reserved STE10/100A Default RW type 000 RO 000 RO 0 RO/LH* 1 ...
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... PMR0 will be set to ‘1’. Aux. current load. These three bits report the maximum 3.3Vaux current requirements for STE10/100A chip. If bit 31 of PMR0 is ‘1’, the default value is 111b, which means the STE10/100A need 375 mA to support remote wake-up in D3cold power state ...
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... Packet”, “Unicast”, and “Muliticast”. Wake on LAN mode enable. When this bit is set to ‘1’, then the STE10/100A enters wake on LAN mode and enters the sleep state. Once the STE10/100A enters the sleep state, it remains there until: the wake up event occurs, the WOL bit is cleared reset (software or hardware) happens ...
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... Data_Scale field. This field is required for any function that implements the data register. The STE10/100A does not support Data_select. PME_En. When set, enables the STE10/100A to assert PME#. When cleared, disables the PME# assertion. Reserved Default ...
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... ADDR 7~0 DATA 56/82 Description PowerState, this two-bit field is used both to determine the current power state of the STE10/100A and to set the STE10/100A into a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported state to this field, the write operation will complete normally on the bus, but the data is discarded and no state change occurs ...
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... STE10/100A Table 8. Control/status register description (continued) Bit # Name CSR25 (offset = a4h), PAR0 - Physical address register 0 automatically recalled from EEPROM 31~24 PAB3 23~16 PAB2 15~8 PAB1 7~0 PAB0 CSR26 (offset = a8h), PAR1 - Physical address register 1 automatically recalled from EEPROM 31~24 --- 23~16 --- 15~8 PAB5 7~0 PAB4 For example, physical address = 00-00-e8-11-22-33 - PAR0 PAR1 PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000) ...
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... Mb/s auto-negotiation on twisted pair” of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status. Note: Since only double word access is supported for register R/W in the STE10/100A, the higher word (bit 31~16) of the XCVR registers (XR0~XR10) should be ignored. Table 9. Transceiver registers list ...
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... STE10/100A transceivers are turned off. reserved Re-start auto-negotiation process control. 1: Auto-negotiation process will be restarted. This bit will be cleared by STE10/100A after the Auto-negotiation has restarted. Full/half duplex mode select. 1: full duplex mode is selected. This bit will be ignored if auto-negotiation is enabled (ANEN, XR0 bit 12) ...
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... REV 60/82 Description 10BASE-T full duplex ability. Always 1, since STE10/100A has 10Base-T full duplex ability. 10BASE-T half duplex ability. Always 1, since STE10/100A has 10Base-T half duplex ability. Reserved Auto-negotiation completed. 0: Auto-negotiation process incomplete. 1: Auto-negotiation process complete. Result of remote fault detection remote fault condition detected. ...
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... LPRF 12,11 --- 10 LPFC Registers and descriptors description Description Next page ability. Always 0; STE10/100A does not provide next page ability. reserved Remote fault function. 1: remote fault function present Reserved Flow control function ability. 1: supports PAUSE operation of flow control for full duplex link. 100BASE-T4 ability. ...
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... Link partner’s next page ability. 0: link partner without next page ability. 1: link partner with next page ability. STE10/100A’s next page ability. Always 0; STE10/100A does not support next page ability. Page received new page has been received new page has been received. ...
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... STE10/100A Table 10. Transceiver registers description (continued) Bit # Name XR7(offset = d0h) - XMC, XCVR mode control 15~12 --- 11 LD 10~0 --- XR8(offset = d4h) - XCIIS, XCVR configuration information and interrupt status 15~10 ---- 9 SPEED 8 DUPLEX 7 PAUSE 6 ANC 5 RFD ANAR 2 PDF 1 ANPR Registers and descriptors description Description Reserved Long distance mode of 10BASE-T. ...
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... Disable the RX_ERR counter. 0: the receive error counter - RX_ERR is enabled. 1: the receive error counter - RX_ERR is disabled. Auto-negotiation completed. This bit is the same as bit 5 of XR1. 0: the auto-negotiation process has not completed yet. 1: the auto-negotiation process has completed. STE10/100A Default RW type 0 RO/LH* 0 R/W 0 R/W 0 ...
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... STE10/100A Table 10. Transceiver registers description (continued) Bit # Name 11, 10 --- 9 ENRLB 8 ENDCR 7 ENRZI 6 --- 5 ISOTX 4~2 CMODE 1 DISMLT 0 DISCRM Registers and descriptors description Description Reserved Enable remote loop-back function. 1: enable remote loop-back (CSR6 bits 11 and 10 must be 00). Enable DC restoration. 0: disable DC restoration. 1: enable DC restoration. ...
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... Registers and descriptors description 4.4 Descriptors and buffer management The STE10/100A provides receive and transmit descriptors for packet buffering and management. 4.4.1 Receive descriptor Table 11. Receive descriptor table 31 RDES0 Own RDES1 RDSE2 RDSE3 Note: Descriptors and receive buffers addresses must be long-word aligned Table 12. ...
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... STE10/100A Table 12. Receive descriptor description (continued) Bit# Name reserved Default = RDES1 31~26 --- 25 RER 24 RCH 23~22 --- 21~11 RBS2 10~ 0 RBS1 RDES2 31~0 RBA1 RDES3 31~0 RBA2 Registers and descriptors description Description First descriptor Last descriptor Packet too long (packet length > 1518 bytes). This bit is valid only in a frame’ ...
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... Error summary. Logical OR of the following bits: 1: under-run error 8: excessive collision 9: late collision 10: no carrier 11: loss carrier 14: jabber time-out Transmit jabber time-out Reserved Loss of carrier No carrier Late collision Excessive collision Heartbeat fail Collision count Reserved Under-run error Deferred Interrupt completed Last descriptor STE10/100A 0 Status Buffer1 byte-count Description ...
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... STE10/100A Table 14. Transmit descriptor description (continued) Bit# Name 29 FS 28,27 --- TER 24 TCH 23 DPD 22 --- 21-11 TBS2 10-0 TBS1 TDES2 31~0 BA1 TDES3 31~0 BA2 Registers and descriptors description Description First descriptor Reserved Disable add CRC function End of ring 2nd address chain. Indicates that the buffer 2 address is the next descriptor ...
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... Description STE10/100A signature: 0x81, 0x09 Format major version: 0x02, old ROM format version 0x01 is for STE10/100A-MAC only. Format minor version: 0x00 Reserved IEEE network address IEEE ID checksum1: Sm =0, carry=0 0 SUM=Sm where Sm =(Sm <<1)+(carry from shift)+ID ...
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... STE10/100A Table 16. Connection type definition Name 0xFFFF 0x0100 0x0200 0x0400 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0010 0x0013 0x0015 General EEPROM format description Description Software driver default Auto-negotiation Power-on auto-detection Auto sense 10BaseT BNC AUI 100BaseTx 100BaseT4 100BaseFx 10BaseT full duplex ...
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... V to VCC + 0 VCC + 0.5 V -65 ° 150 ° C(-85° 302° F) 0° 70° C (32° 158° F) 2000V Parameter Test condition Vin =.8V Vin = 2.0V Iout =3mA/6mA Iout =-2mA Iout=3mA,6mA Iout=-2mA STE10/100A Value Min. Typ. Max. Units 3.14 3.3 3.46 V 130 mA -0.5 ...
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... STE10/100A Table 18. General DC specifications (continued) Symbol 10BASE-T voltage/current characteristics Input differential accept peak Vida10 voltage Input differential reject peak Vidr10 voltage Output differential peak Vod10 voltage 100BASE-TX voltage/current Characteristics Input differential accept peak Vida100 voltage Input differential reject peak Vidr100 voltage ...
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... Trst stable Reset active time after clk Trst-clk stable Reset active to output float Trst-off delay 74/82 0.6Vcc 0.475Vcc 0.4Vcc 0.325Vcc 0.2Vcc Parameter Test condition Parameter Test condition STE10/100A 0.4Vcc, p-to-p minimum Min. Typ. Max. Units PPM Min. Typ. Max. ...
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... STE10/100A Figure 17. PCI timings INPUT Table 23. Flash interface timings Symbol Tfcyc Read/write cycle time Address to read data setup Tfce time Tfce CS# to read data setup time OE# active to read data Tfoe setup time OE# inactive to data driven Tfdf delay time Address setup time before ...
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... Hold time of DI after SK Tecsl CS low time 76/82 Tfcyc Tahw Tfasw Tfah Tfasc CS# Tfcss Tfwpw WE# Tfwph DATA Tfcyc CS# Tfce OE# Tfoe Tfasd DATA Parameter Test condition Tscf - 1.4 µs STE10/100A Tfcsh Tfds Tfdh Tfdf Min. Typ. Max. 714 0.1 1.7 200 650 200 600 0 700 0.5 1.1 Units kHz µ ...
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... STE10/100A Figure 20. Serial EEPROM timings CS CLK DI Table 25. 10BASE-T normal link pulse (NLP) timings specifications Symbol Tnpw NLP width Tnpc NLP period Figure 21. Normal link pulse timings Table 26. Auto-negotiation fast link pulse (FLP) timings specifications Symbol Tflpw FLP Width Clock pulse to clock pulse ...
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... Electrical specifications and timings Figure 22. Fast link pulse timings Table 27. 100BASE-TX transmitter AC timings specification Symbol TDP-TDN differential output Tjit peak jitter 78/82 Tflcpp Tflcpd Tflpw Tflbp Tflbw Parameter Test condition STE10/100A Min. Typ. Max. Units 1.4 ps ...
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... STE10/100A 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... PQF128CM OUTLINE AND MECHANICAL DATA PQFP128 (14x20x2.7mm) CDC ZE 0. .005 E HE 0.7 DEGREES 0.25 GAGE PLANE STE10/100A 1020818 ...
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... STE10/100A 8 Ordering information Table 28. Order codes Part number E-STE10/100A 9 Revision history Table 29. Document revision history Date 06-Nov-2002 28-Feb-2007 PQFP128 (14mm x 20mm x 2.7mm) Revision 7 Previous release (as revision A07) Removed the STE10/100E order code and updated the ordering 8 information. Ordering information Package Changes 81/82 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 82/82 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STE10/100A ...