S1D13700F01 Epson Electronics America, Inc., S1D13700F01 Datasheet
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S1D13700F01 Summary of contents
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... S1D13700F01 Embedded Memory Graphics LCD Controller Hardware Functional Specification Document Number: X42A-A-002-04 Status: Revision 4.05 Issue Date: 2005/12/13 © SEIKO EPSON CORPORATION 2004 - 2005. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13700F01 X42A-A-002-04 Epson Research and Development Revision 4.05 Vancouver Design Center Hardware Functional Specification Issue Date: 2005/12/13 ...
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... MC68K Family Bus Direct/Indirect Interface with DTACK# Timing . . . . . . . . 30 7.3.4 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing . . . . . . 32 7.3.5 M6800 Family Bus Indirect Interface Timing . . . . . . . . . . . . . . . . . . . . 34 7.3.6 Display Memory Access Timing for Text Mode . . . . . . . . . . . . . . . . . . . 36 7.4 Power Save Mode/Display Enable Timing . . . . . . . . . . . . . . . . . . . 37 Hardware Functional Specification Issue Date: 2005/12/13 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision 4.05 Page 3 S1D13700F01 X42A-A-002-04 ...
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... Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12 Display Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 12.1 Character Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .77 12.2 Screen Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 12.2.1 Screen Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.2.2 Display Address Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.2.3 Display Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.3 Cursor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 12.3.1 Cursor Write Register Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 S1D13700F01 X42A-A-002-04 Epson Research and Development Revision 4.05 Vancouver Design Center Hardware Functional Specification Issue Date: 2005/12/13 ...
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... Layered Display Attributes . . . . . . . . . . . . . . . . . . . . . . . . . 118 15.4.1 Inverse Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 15.4.2 Half-Tone Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 15.4.3 Flash Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 15 16-Dot Graphic Display 15.5.1 Command Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 15.5.2 Kanji Character Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16 Internal Character Generator Font Hardware Functional Specification Issue Date: 2005/12/ 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 . . . . . . . . . . . . . . . . . . . . . . . . 116 . . . . . . . . . . . . . . . . . . . . . . . . 121 . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Revision 4.05 Page 5 S1D13700F01 X42A-A-002-04 ...
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... Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 20 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 20.1 Epson LCD Controllers (S1D13700F01) 20.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 S1D13700F01 X42A-A-002-04 Epson Research and Development ...
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... We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com. 1.2 Overview Description The S1D13700F01 can display both text and graphics on an LCD panel. The S1D13700F01 allows layered text and graphics, scrolling of the display in any direction, and partitioning of the display into multiple screens. It includes 32K bytes of embedded SRAM display memory which is used to store text, character codes, and bit-mapped graphics ...
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... Three overlapping screens in graphics mode • Programmable cursor control • Smooth horizontal scrolling of all or part of the display in monochrome mode • Smooth vertical scrolling of all or part of the display in all modes S1D13700F01 X42A-A-002-04 Epson Research and Development Revision 4.05 Vancouver Design Center ...
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... 2.7 Clock Source • Two terminal crystal or Single Oscillator input Input Clock (maximum 60 MHz) FPSHIFT Clock (maximum 15 MHz) 2.8 Package • TQFP13 - 64-pin Pb-free package (lead free) Hardware Functional Specification Issue Date: 2005/12/13 3.0 to 3.6 volts DD 3.0 to 5.5 volts Revision 4.05 Page 9 S1D13700F01 X42A-A-002-04 ...
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... Page 10 3 System Diagrams Generic Bus (Indirect) CS# Axx A0 D[15:8] D[7:0] RD0# RD1# WR0# WR1# WAIT# RESET# Figure 3-1 Indirect Generic to S1D13700F01 Interface Example Generic Bus (Direct) CS# A[15:0] D[15:8] D[7:0] RD0# RD1# WR0# WR1# WAIT# RESET# Figure 3-2 Direct Generic to S1D13700F01 Interface Example S1D13700F01 X42A-A-002-04 S1D13700F01 CNF4 AS# ...
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... Epson Research and Development Vancouver Design Center MC68K (Indirect) AS# FC[2:0] A[23:1] A0 D[15:8] D[7:0] UDS# LDS# R/W# DTACK# RESET# Figure 3-3 Indirect MC68K to S1D13700F01 Interface Example MC68K (Direct) AS# FC[2:0] A[23:16] A[15:0] D[15:8] D[7:0] UDS# LDS# R/W# DTACK# RESET# Figure 3-4 Direct MC68K to S1D13700F01 Interface Example Hardware Functional Specification Issue Date: 2005/12/13 S1D13700F01 CNF4 AS# ...
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... Page 12 M6800 (Indirect) VMA# A[16:1] A0 D[15:8] D[7:0] E R/W# RESET# Figure 3-5 Indirect M6800 to S1D13700F01 Interface Example S1D13700F01 X42A-A-002-04 S1D13700F01 CNF4 AS# Decoder CS# A[15:1] A0 (command or parameter) D[7:0] RD# WR# WAIT# RESET# /RESET Revision 4.05 Epson Research and Development Vancouver Design Center CNF3 CNF2 Hardware Functional Specification Issue Date: 2005/12/13 ...
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... Address Generator Controller Hardware Functional Specification Issue Date: 2005/12/13 LCD Character Generator LCD Controller ROM Layered Layered GrayScale Controller FRM Controller Microprocessor Interface Host Microprocessor Figure 4-1 Functional Block Diagram Revision 4.05 Page 13 DotClock Generator Internal Clock Dot Counter Oscillator S1D13700F01 X42A-A-002-04 ...
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... VSS WAIT# HIOVDD CNF0 CNF1 CNF2 CNF3 CNF4 AS# A15 A14 A13 64 1 Figure 5-1 Pinout Diagram (TQFP13 - 64 pin) S1D13700F01 X42A-A-002-04 D1370001A1 Index Revision 4.05 Epson Research and Development Vancouver Design Center 33 NIOVDD 32 YDIS FPFRAME YSCL VSS MOD FPLINE COREVDD XECL FPSHIFT ...
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... Output buffer (6mA/-6mA@3.3V) with Test LIN TTL transparent input LOT TTL transparent output T1 Test mode control input with pull-down resistor (typical value of 50 kΩ@3.3V) HTB2T Tri-state output buffer (6mA/-6mA@3.3V) Hardware Functional Specification Issue Date: 2005/12/13 Table 5-1: Cell Descriptions Description Revision 4.05 Page 15 S1D13700F01 X42A-A-002-04 ...
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... M6800 family of processors (such as the 6800). For further information, see Section 5.3, “Summary of Configuration Options” on page 20. This input pin selects the microprocessor addressing mode and must be connected to either HIOVDD or VSS. The S1D13700F01 HIOVDD — supports both Direct and Indirect addressing modes. For further information, see Section 5.3, “ ...
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... When the M6800 host bus interface is selected, this signal is the read/write control signal (R/W#). Data is read from the HIOVDD — S1D13700F01 if this signal is high, and written to the S1D13700F01 low. • When the MC68K host bus interface is selected, this signal is the read/write control signal (RD/WR#). Data is read from the S1D13700F01 if this signal is high, and written to the S1D13700F01 low ...
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... Page 18 5.2.2 LCD Interface In order to provide effective low-power drive for LCD matrixes, the S1D13700F01 can directly control both the X and Y-drivers using an enable chain. Pin Name Type Pin # Cell FPDAT[3:0] O 18-21 OB2T (XD[3:0]) FPSHIFT O 23 OB2T (XSCL) XECL O 24 OB2T FPLINE O 26 OB2T (LP) ...
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... State — — IO power supply for the Host (MPU) interface, 3.3/5.0 volts. — — IO power supply for the LCD interface, 3.3/5.0 volts. — — Core power supply, 3.3 volts. — — Ground for HIOVDD, NIOVDD, and COREVDD Revision 4.05 Page 19 Description Description S1D13700F01 X42A-A-002-04 ...
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... CNF3 CNF2 0 CNF[3: Select the FPSHIFT cycle time (FPSHIFT:Clock Input) as follows: CNF1 CNF0 0 CNF[1: S1D13700F01 X42A-A-002-04 Table 5-6: Summary of Configuration Options Configuration State DIrect Addressing Mode: Host Bus 0 Generic Bus 1 Reserved 0 M6800 Family Bus Interface 1 MC68K Family Bus Interface ...
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... HIOVDD HIOVDD Connected to Connected to Connected to VSS HIOVDD HIOVDD See Note See Note See Note Revision 4.05 Page 21 M6800 M6800 Direct Indirect Connected to VSS A0 D[7:0] External Decode Connected to HIOVDD E Not R/W# supported Unconnected RESET# Connected to HIOVDD Connected to HIOVDD Connected to VSS See Note S1D13700F01 X42A-A-002-04 ...
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... High Level Input Voltage IH1 V Low Level Input Voltage IL1 V High Level Input Voltage T+ V Low Level Input Voltage T- V Hysteresis Voltage H1 R Pull Down Resistance PD S1D13700F01 X42A-A-002-04 Table 6-1 Absolute Maximum Ratings Rating V - 0 0 ...
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... V -0.4 DD ⎯ ⎯ 0.4 ⎯ ⎯ 3.5 ⎯ ⎯ 1.0 ⎯ 2.0 4.0 ⎯ 0.8 3.1 ⎯ ⎯ 0 144 Cell Type OB2T CB2 HTB2T CI CID1 CB2 SI SI CID1 S1D13700F01 X42A-A-002-04 Page 23 Units μA μA μA μ kΩ ...
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... Input Clock Rise Time (10% - 90%) r Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI. For further details on internal clocks, see Sec- tion 9, “Clocks” on page 42. S1D13700F01 X42A-A-002-04 Core V = 3.3V ± 10 3.3V ± 10% or 5.0V ± 10% ...
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... For indirect mode, writing the SYSTEM SET command will exit power save mode and start the internal oscillator. 2. The S1D13700F01 requires a reset pulse of at least 1 ms after power-on in order to re-initialize its internal state. For maximum reliability not recommended to apply a DC voltage to the LCD panel while the S1D13700F01 is reset ...
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... Page 26 7.3 CPU Interface Timing 7.3.1 Generic Bus Direct/Indirect Interface with WAIT# Timing CS# A[15:0] WR#, RD# WAIT# D[7:0] (write) D[7:0] (read) Figure 7-4 Generic Bus Direct/Indirect Interface with WAIT# Timing S1D13700F01 X42A-A-002- t13 t4 Valid t11 t5 Revision 4.05 Epson Research and Development Vancouver Design Center t6 t7 t12 t8 t9 ...
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... Note 2 Note 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ Note 5 Note 5 S1D13700F01 X42A-A-002-04 Page 27 Units ...
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... Page 28 7.3.2 Generic Bus Direct/Indirect Interface without WAIT# Timing CS# A[15:0] WR#, RD# D[7:0] (write) D[7:0] (read) Figure 7-5 Generic Bus Direct/Indirect Interface without WAIT# Timing S1D13700F01 X42A-A-002- t10 t11 t3 Valid t4 t9 Revision 4.05 Epson Research and Development Vancouver Design Center t5 t6 t12 t7 t8 Valid Hardware Functional Specification ...
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... Note 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ ⎯ ⎯ Note 5 Note 5 S1D13700F01 X42A-A-002-04 Page 29 Units ...
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... Page 30 7.3.3 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing CS# A[15:0], WR# (RW#, MR#) AS# RD# (UDS#, LDS#) WAIT# (DTACK#) D[7:0] (write) D[7:0] (read) Figure 7-6 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing S1D13700F01 X42A-A-002- t14 t3 t13 t4 t11 t5 Revision 4.05 Epson Research and Development Vancouver Design Center ...
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... Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ Note 5 Note 5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 6 0 Note 6 S1D13700F01 X42A-A-002-04 Page 31 Units ...
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... Page 32 7.3.4 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing CS# A[15:0], WR# (RW#, MR#) AS# RD# (UDS#, LDS#) D[7:0] (write) D[7:0] (read) Figure 7-7 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing S1D13700F01 X42A-A-002- t13 t10 t11 Revision 4.05 Epson Research and Development Vancouver Design Center ...
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... Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ ⎯ ⎯ Note 5 Note 5 ⎯ ⎯ ⎯ ⎯ S1D13700F01 X42A-A-002-04 Page 33 Units ...
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... Page 34 7.3.5 M6800 Family Bus Indirect Interface Timing CS# A[15:0], WR# (RW#) RD# (E) D[7:0] (write) D[7:0] (read) Figure 7-8 M6800 Family Bus Indirect Interface Timing S1D13700F01 X42A-A-002- t10 t11 Revision 4.05 Epson Research and Development Vancouver Design Center t5 t6 t12 t7 t8 Hardware Functional Specification Issue Date: 2005/12/13 ...
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... Note 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 3 Note 3 ⎯ ⎯ Note 4 Note 4 ⎯ ⎯ ⎯ ⎯ Note 5 Note 5 S1D13700F01 X42A-A-002-04 Page 35 Units ...
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... For 1 bpp, use the following formula: ((TCR + DIV tOSC For 2 bpp, use the following formula: ((TCR + DIV tOSC For 4 bpp, use the following formula: ((TCR + DIV tOSC S1D13700F01 X42A-A-002-04 Note 3 Memory Access ...
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... Hardware Functional Specification Issue Date: 2005/12/13 t1 Display Off or Power Save Mode Enabled 3.0 Volt Min. ⎯ ⎯ 1Ts + 10 ⎯ 2Ts + 10 ⎯ 2Ts + 10 Revision 4.05 Page 37 t2 Display On 5.0 Volt Units Max. Min. Max. ⎯ Frames ⎯ 1Ts + 10 ⎯ 2Ts + 10 ⎯ 2Ts + 10 S1D13700F01 X42A-A-002- ...
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... FPLINE (LP) MOD (WF) FPDAT[3:0] Invalid YSCL MOD YSCL FPLINE (LP) HNDP FPSHIFT (XSCL) FPDAT3 Invalid FPDAT2 Invalid FPDAT1 Invalid FPDAT0 Invalid XECL S1D13700F01 X42A-A-002-04 VDP (1 Frame) LINE1 LINE2 LINE3 LINE4 1 Line HDP 1-1 1-5 1-2 1-6 1-3 1-7 1-4 1-8 Figure 7-11: Monochrome 4-Bit Panel Timing Revision 4.05 Epson Research and Development ...
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... Epson Research and Development Vancouver Design Center FPSHIFT (XSCL) FPDAT3 FPDAT2 FPDAT1 FPDAT0 FPLINE (LP) XECL MOD (WF(B)) FPFRAME (YD) YSCL Hardware Functional Specification Issue Date: 2005/12/ t11 t12 t13 t15 t16 Revision 4.05 Page 39 t10 t14 S1D13700F01 X42A-A-002-04 ...
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... FPFRAME falling edge hold time from YSCL falling edge t16 YSCL pulse width FPSHIFT cycle time = 4Ts when CNF[1: 8Ts when CNF[1: 16Ts when CNF[1: t10min = 0.25Tc - 8 S1D13700F01 X42A-A-002-04 Epson Research and Development 3.3 Volts Min Max ⎯ 1 ⎯ ...
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... Epson Research and Development Vancouver Design Center 8 Memory Mapping The S1D13700F01 includes 32K bytes of embedded SRAM. The memory is used for the display data, the registers and the CGROM. 0000h 7FFFh 8000h 802Fh 8030h FFFFh Hardware Functional Specification Issue Date: 2005/12/13 (MSB) ...
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... Page 42 9 Clocks 9.1 Clock Diagram The following figure shows the clock tree of the S1D13700F01. CLKI Internal OSC Power Save Mode (REG[08h] bit 0) FPSHIFT Cycle Time (CNF[1:0] see Note) Note The FPSHIFT Cycle Time is configured using the CNF[1:0] pins. For further informa- tion, see Section 5.3, “ ...
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... Diagram,” on page 42. The maximum frequency possible for FPSHIFT clock is 15MHz. 9.3 Oscillator Circuit The S1D13700F01 design incorporates an oscillator circuit. A stable oscillator can be constructed by connecting an AT-cut crystal, two capacitors, and two resistors to XCG1 and XCD1, as shown in the figure below. If the oscillator frequency is increased, Cd and Cg should be decreased proportionally ...
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... Page 44 10 Registers 10.1 Register Set The S1D13700F01 registers are listed in the following table. Register REG[00h] Memory Configuration Register REG[02h] Vertical Character Size Register REG[04h] Total Character Bytes Per Row Register REG[06h] Horizontal Address Range Register 0 REG[08h] Power Save Mode Register REG[09h] Display Enable Register ...
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... Section 15.1.2, “Initialization Example” on page 105. SYSTEM SET The SYSTEM SET command is used to configure the S1D13700F01 for the display used and to exit power save mode when indirect addressing is used. The values from REG[00h] through REG[07h] are passed as parameters when the SYSTEM SET command is issued. For further information on the SYSTEM SET command, see Section 11.1.1, “ ...
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... This bit causes the S1D13700F01 to offset the text screen against the graphics back layer by one vertical pixel. To shift the text screen horizontally, the horizontal pixel scroll function (REG[1Bh] or the HDOT SCR command for indirect addressing) can be used to shift the text screen pixels to the right ...
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... The following diagrams show examples of the possible drive methods. XECL FPFRAME Y driver Hardware Functional Specification Issue Date: 2005/12/13 XECL X driver FPFRAME Y driver LCD Figure 10-2 Single Drive Panel Display X driver Upper Panel Lower Panel X driver Figure 10-3 Dual Drive Panel Display Revision 4.05 X driver X driver X driver S1D13700F01 X42A-A-002-04 Page 47 ...
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... When this bit = 0, the internal CGROM is selected. When this bit = 1, the internal CGRAM is selected. Note If the CGRAM is used (includes CGRAM1 and CGRAM2), only 1 bpp is supported. S1D13700F01 X42A-A-002-04 Table 10-2 LCD Parameter Summary REG[00h] bit (IV) REG[00h] bit (IV) ...
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... These bits define the horizontal size, or width, of each character, in pixels. REG[01h] bits 3-0 = Horizontal Character Size in pixels - 1 The S1D13700F01 handles display data in 8-bit units, therefore characters larger than 8 pixels wide must be formed from 8-pixel segments. The following diagram shows an example of a character requiring two 8-pixel segments where the remainder of the second eight bits are not displayed ...
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... Section 15.1.1, “SYSTEM SET Command and Parameters” on page 102. TC/R can be adjusted to hold the frame period constant and minimize jitter for any given main oscilla- tor frequency, fosc. REG[04h] bits 7-0 = [TC/ Note TC/R must be programmed such that the following formulas are valid. S1D13700F01 X42A-A-002- Character Bytes Per Row bits 7-0 ...
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... Figure 10-5 Horizontal Address Range and Character Bytes Per Row Relationship Hardware Functional Specification Issue Date: 2005/12/13 Frame Height bits 7 Horizontal Address Range bits 7 Horizontal Address Range bits 15 Display area C/R Display memory limit AP Revision 4.05 Page 51 Read/Write Read/Write Read/Write S1D13700F01 X42A-A-002-04 ...
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... Page 52 POWER SAVE The POWER SAVE command is used to enter power save mode on the S1D13700F01 when indirect addressing is used. For further information on the POWER SAVE command, see Section 11.1.2, “POWER SAVE” on page 72. Note When indirect addressing is used, the SYSTEM SET command is used to exit power save mode. For further information on the SYSTEM SET command, see Section 11.1.1, “ ...
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... Table 10-3 Screen Block 3 Attribute Selection Third Screen Block (SAD3) REG[0Ah] bit Revision 4.05 Read/Write Display Enable 2 1 Read/Write Cursor Attribute bits 1 Attributes OFF (Blank) No Flashing Flash (approx. 2 Hz) Flash (approx. 16 Hz) S1D13700F01 X42A-A-002-04 Page ...
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... When the cursor is disabled, a write to memory automatically enables the cursor and places the cursor at the next memory location. A read from memory does not enable the cursor, however, it still places the cursor at the next memory location. S1D13700F01 X42A-A-002-04 Second Screen Block (SAD2, SAD4) ...
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... Table 10-7 “Display Modes,” on page 58. Hardware Functional Specification Issue Date: 2005/12/13 Screen Block 1 Start Address bits 7-0 (LSB Screen Block 1 Start Address bits 15-8 (MSB Screen Block 1 Size bits 7 Revision 4.05 Page 55 Read/Write Read/Write Read/Write S1D13700F01 X42A-A-002-04 ...
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... These bits determine the size of screen block 2, in lines. REG[10h] bits 7-0 = screen block 2 size in number of lines - 1 Note The relationship between the screen block start address (SADx), screen block size (SLx), and the display mode is described in Table 10-7 “Display Modes,” on page 58. S1D13700F01 X42A-A-002-04 Screen Block 2 Start Address bits 7-0 (LSB ...
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... Screen Block 3 Start Address bits 7-0 (LSB Screen Block 3 Start Address bits 15-8 (MSB Screen Block 4 Start Address bits 7-0 (LSB Screen Block 4 Start Address bits 15-8 (MSB Revision 4.05 Page 57 Read/Write Read/Write Read/Write Read/Write S1D13700F01 X42A-A-002-04 ...
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... SAD1 0 SL1 SAD3 First Screen Block Second Screen Block SAD2 SAD1 1 SL1 SAD3 S1D13700F01 X42A-A-002-04 Table 10-7 Display Modes First Layer SAD1 SL1 SAD3 (see note 1) Set both SL1 and SL2 to L not using a partitioned screen. Screen Configuration Example SL2 Graphics display page 2 ...
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... SL1 = L Screen Configuration Example SAD3 SAD2 SAD1 SL1 Graphics display page 1 Layer 3 Layer 1 Layer 2 Revision 4.05 Second Layer SAD2, SL2 SAD3 (see note 2) (SAD3) Second Layer Third Layer SAD2, SAD3 SL2 = L Graphics display page 3 SL2 Graphics display page 2 S1D13700F01 X42A-A-002-04 Page 59 ...
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... SL1 = screen block 1 size (REG[0Dh] bits 7-0) L/F = (REG[05h] bits 7-0) CSRFORM The CSRFORM command is used to configure the S1D13700F01 cursor when indirect addressing is used. The values from REG[15h] through REG[16h] are passed as parameters when the CSRFORM command is issued. For further information on the CSRFORM command, see Section 11.1.5, “CSRFORM” on page 73. ...
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... The vertical cursor size must be less than or equal to the vertical character size. (REG[16h] bits 3-0 <= REG[02h] bits 3-0) Hardware Functional Specification Issue Date: 2005/12/ n selected. Revision 4.05 Page 61 Read/Write Cursor Width bits 3 Read/Write Cursor Height bits 3 S1D13700F01 X42A-A-002-04 ...
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... Note The cursor moves in address units even if horizontal character size is equal to 9 (REG[01h] bits 3-0 = 9), therefore the cursor address increment must be preset for movement in character units. For further information, see Section 12.3, “Cursor Con- trol” on page 84. S1D13700F01 X42A-A-002-04 n – ...
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... When this bit = 1, screen block 1 is configured for graphics mode. Note Screen blocks 2 and 4 can display graphics only. Hardware Functional Specification Issue Date: 2005/12/13 3 Layer Overlay Screen Block 3 Select Display Mode Revision 4.05 Read/Write Screen Block 1 Layer Composition Method bits 1-0 Display Mode S1D13700F01 X42A-A-002-04 Page 63 ...
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... L3: Third layer (graphics only) Layer 1 1 EPSON 2 EPSON 3 EPSON Figure 10-9 Combined Layer Display Examples Note L1: Not flashing L2: Flashing L3: Flashing S1D13700F01 X42A-A-002-04 Table 10-9 Composition Method Selection Composition Method ∪ ∪ Underlining, rules, mixed text and graphics ⊕ ∪ L2) ...
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... The character starts in RAM at address 6400h and takes 8 memory locations. Hardware Functional Specification Issue Date: 2005/12/13 CGRAM Start Address bits 7-0 (LSB CGRAM Start Address bits 15-8 (MSB (80h 6000h = 400h + 6000h = 6400h Revision 4.05 Page 65 Read/Write Read/Write S1D13700F01 X42A-A-002-04 ...
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... REG[03h] bits 7-0, must be set to one more than the actual number of horizontal characters before using horizontal pixel scroll. Smooth scrolling can be simu- lated by repeatedly changing the value of REG[1Bh] bits 2-0. See Section 12.5.6, “Hori- zontal Pixel Scrolling (HDOTSCR)” on page 95 for more information on scrolling the display. S1D13700F01 X42A-A-002-04 n ...
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... If a new address is not set, display memory accesses are from the last set address or the address after previous automatic increments. Hardware Functional Specification Issue Date: 2005/12/13 Cursor Write bits 7-0 (LSB Cursor Write bits 15-8 (MSB Revision 4.05 Page 67 Write Only Write Only S1D13700F01 X42A-A-002-04 ...
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... These bits indicate the memory address where the cursor is currently located. After issuing the command, the data read address is read twice. Once for the low byte and then again for the high byte of the register. S1D13700F01 X42A-A-002-04 Cursor Read bits 7-0 (LSB) ...
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... The horizontal character size (REG[01h] bits 3-0) must be set to 7h and the Horizontal Pixel Scroll bits (REG[1Bh] bits 2-0) must be set to 0. Hardware Functional Specification Issue Date: 2005/12/13 n Table 10-10 Bit-Per-Pixel Selection REG[20h] bits 1-0 Bits-Per-Pixel Reserved Revision 4.05 Page 69 Read/Write Bit-Per-Pixel Select bits 1 S1D13700F01 X42A-A-002-04 ...
Page 70
... Table 11-3 M6800 Indirect Addressing Command/Write/Read A0 R Table 11-4 M68K Indirect Addressing Command/Write/Read A0 R/W LDS S1D13700F01 X42A-A-002-04 Table 11-1 Indirect Addressing Command Set Register Description Enables/disables display and display attributes Sets screen block start addresses and sizes Sets cursor type Sets direction of cursor movement OVLAY ...
Page 71
... See Section , “SYSTEM SET” on page 45 for further information. Note If the S1D13700F01 is in power save mode (at power up or after a POWER SAVE com- mand), the SYSTEM SET command will exit power save mode. After writing the SYS- TEM SET command and its 8 parameters, the S1D13700F01 will be in normal operation ...
Page 72
... The following parameters are used for the DISP OFF command. For further details, see Section , “DISP ON/OFF” on page 53. Table 11-8 DISP OFF Command and Parameters MSB bit 7 bit S1D13700F01 X42A-A-002-04 Table 11-6 POWER SAVE Command bit 6 bit 5 bit 4 bit 3 bit 2 ...
Page 73
... REG[15h] bits 3 REG[16h] bits 3 Revision 4.05 Indirect C REG[0Bh] bits 7-0 P1 REG[0Ch] bits 7-0 P2 REG[0Dh] bits 7-0 P3 REG[0Eh] bits 7-0 P4 REG[0Fh] bits 7-0 P5 REG[10h] bits 7-0 P6 REG[11h] bits 7-0 P7 REG[12h] bits 7-0 P8 REG[13h] bits 7-0 P9 REG[14h] bits 7-0 P10 LSB bit 0 Indirect S1D13700F01 X42A-A-002-04 Page 73 ...
Page 74
... See “CGRAM ADR” on page 65 for further information. Table 11-13 CGRAM ADR Command and Parameters MSB bit 7 bit 6 bit A15 A14 A13 S1D13700F01 X42A-A-002-04 Table 11-11 CSRDIR Command bit 5 bit 4 bit 3 bit 2 REG[17h] bits 1 bit 5 bit 4 bit 3 ...
Page 75
... A13 A12 A11 A10 A9 A8 LSB bit 4 bit 3 bit 2 bit 1 bit A12 A11 A10 A9 A8 Revision 4.05 LSB bit 0 Indirect Indirect 0 C (CSRL) P1 (CSRH) P2 Indirect C (CSRL) P1 (CSRH) P2 S1D13700F01 X42A-A-002-04 Page 75 ...
Page 76
... Page 76 11.1.12 GRAYSCALE See Section , “GRAYSCALE” on page 69 for further information. Table 11-17 Gray Scale Command and Parameters MSB bit 7 bit 11.1.13 Memory Control See “Drawing Control Registers” on page 67 for further information. S1D13700F01 X42A-A-002-04 bit 5 bit 4 bit 3 bit 2 bit ...
Page 77
... Space data Space data ≤ 8) S1D13700F01 X42A-A-002-04 Page 77 ...
Page 78
... Figure 12-2 Character Width Greater than One Byte Wide ([FX Note The S1D13700F01 does not automatically insert spaces between characters. If the dis- played character size is 8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row, even though the character image requires only one ...
Page 79
... Vancouver Design Center 12.2 Screen Configuration 12.2.1 Screen Configuration The S1D13700F01 can be configured for a single text screen, overlapping text screens, or overlapping graphics screens. Graphics screens use eight times as much display memory as a text screen in 1 bpp. Figure 12-3 shows the relationship between the virtual screens and the physical screen ...
Page 80
... Page 80 12.2.2 Display Address Scanning The S1D13700F01 scans the display memory in the same way as a raster scan CRT screen. Each row is scanned from left to right until the address range equals C/R, REG[03h] bits 7- 0. Rows are scanned from top to bottom. When in graphics mode, at the start of each line the address counter is set to the address at the start of the previous line plus the horizontal address range (or address pitch), REG[06h] - REG[07h] ...
Page 81
... In 2 bpp, 1 byte corresponds to 4 pixels bpp, 1 byte corresponds to 2 pixels. Hardware Functional Specification Issue Date: 2005/12/13 SAD + 2 SAD + C/R SAD + AP SAD + C/R Revision 4.05 Page 81 SAD SAD +1 SAD + 2 Line 1 SAD + C/R SAD + AP SAD + Line 2 SAD + AP + C/R SAD + 2AP Line 3 S1D13700F01 X42A-A-002- ...
Page 82
... Assumes REG[00h] bit REG[01h] bits 3 REG[02h] bits 3 Figure 12-6 Dual Panel Display Address Indexing in Text Mode Note In dual panel drive, the S1D13700F01 reads line 1a and line 1b as one cycle. The upper and lower panels are thus read alternately, one line at a time. S1D13700F01 ...
Page 83
... Epson Research and Development Vancouver Design Center 12.2.3 Display Scan Timing During display scanning, the S1D13700F01 pauses at the end of each line for TC/R - C/R ((REG[04h] bits 7-0) - (REG[03h] bits 7-0)) display memory read cycles, although the LCD drive signals are still generated. TC/R may be set to any value within the constraints imposed by C/R, Input Clock (CLK used to fine tune the frame frequency ...
Page 84
... Cursor Display Layers Although the S1D13700F01 can display up to three layers, the cursor is displayed in only one of these layers. For a two layer configuration (REG[18h] bit 4 = 0), the cursor is displayed in the first layer (L1). For a three layer configuration (REG[18h] bit 4 = 1), the cursor is displayed in the third layer (L3) ...
Page 85
... Epson Research and Development Vancouver Design Center Although the cursor is normally displayed for character data, the S1D13700F01 may also display a dummy cursor for graphical characters. This is only possible if a graphics screen is displayed, the text screen is turned off, and the microprocessor generates the cursor control address ...
Page 86
... Memory to Display Relationship The S1D13700F01 supports virtual screens that are larger than the physical size of the LCD panel address range (C/R), REG[03h] bits 7-0. A layer of the S1D13700F01 can be considered as a window into the larger virtual screen held in display memory. This window can be divided into two blocks, with each block able to display a different portion of the virtual screen ...
Page 87
... CGRAM SAD1 C/R Character page 1 C/R SAD3 Character page 3 C/R SAD2 Graphics page 2 C/R SAD3 Graphics page 3 C/R SAD2 Graphics page 2 C/R SAD1 Graphics page 1 Revision 4.05 Page 87 REG[00h] bit SAD1 Display page 1 SAD3 Display page 3 Layer 1 SAD2 SAD4 Display page 2 Display page 4 Layer 2 S1D13700F01 X42A-A-002-04 ...
Page 88
... CRY = cursor height is 16 pixels (REG[16h] bits 3-0) C/R = character bytes per row is 240 bytes (REG[03h] bits 7-0) L/F = frame height is 256 (REG[05h] bits 7- horizontal address range (or address pitch) is 64K bytes (REG[06h] bits 7-0, REG[07h] bits 7-0) Figure 12-12 Virtual Display (Display Window to Memory Relationship) S1D13700F01 X42A-A-002-04 AP CRY CRX C/R Revision 4 ...
Page 89
... 02FF 0080 (MSB) D7 1FFF D7 D0 01110000 #4800 70h 10001000 1 88h 10001000 2 88h 10001000 3 88h 11111000 4 F8h 10001000 5 88h 10001000 6 88h 00000000 #4807 00h Example of character A Revision 4.05 Page 89 ABC XY Display (LSB)(MSB) (LSB Magnified image S1D13700F01 X42A-A-002-04 ...
Page 90
... On-Page Scrolling The normal method of scrolling within a page is to move the whole display up one line and erase the bottom line. However, the S1D13700F01 does not automatically erase the bottom line must be erased with blanking data when changing the scroll address register. ...
Page 91
... SADx = start address of screen block horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Hardware Functional Specification Issue Date: 2005/12/13 SAD1 789 789 SAD1 Figure 12-15 Inter-Page Scrolling Revision 4.05 Page 91 Display memory AP C/R ABC WXYZ 789 ABC WXYZ 789 S1D13700F01 X42A-A-002-04 ...
Page 92
... BC After scrolling 23 Where: SADx = start address of screen block horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Figure 12-16 Horizontal Wraparound Scrolling S1D13700F01 X42A-A-002-04 Display XYZ SAD1 XYZ1 SAD1 Revision 4.05 Epson Research and Development Vancouver Design Center ...
Page 93
... AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Hardware Functional Specification Issue Date: 2005/12/ 1234 56 Figure 12-17 Bi-Directional Scrolling Revision 4.05 Display memory AP BC EFG TUV 12 34 567 C/R 89 ABC E FG TUV 1234 S1D13700F01 X42A-A-002-04 Page 93 ...
Page 94
... The following table summarizes the units, or steps, that can be scrolled for each mode. Mode Text Graphics Note In a divided screen, each block cannot be independently scrolled horizontally in pixel units. S1D13700F01 X42A-A-002-04 Table 12-1 Scrolling Unit Summary Vertical Characters Pixels Revision 4.05 Epson Research and Development ...
Page 95
... Issue Date: 2005/12/13 Case 3 Line 1 Line 2 Where: [CR [TCR [AP HDOTSCR = Enable FPSHIFT = 3 CLK Case 4 Line 1 D Line 2 H Where: [CR [TCR [AP HDOTSCR = Enable FPSHIFT = 3 CLK Revision 4.05 Page S1D13700F01 X42A-A-002-04 ...
Page 96
... CG Characteristics 13.1.1 Internal Character Generator The internal character generator is recommended for minimum system configurations containing a S1D13700F01, display RAM, LCD panel, single-chip microprocessor and power supply. Since the internal character generator uses a CMOS mask ROM also recommended for low-power applications. • pixel font (See Section 16, “Internal Character Generator Font” on page 125) • ...
Page 97
... VA7 Revision 4.05 Page VA6 VA5 VA4 VA3 VA2 VA1 VA0 VA6 VA5 VA4 VA3 VA2 VA1 VA0 S1D13700F01 X42A-A-002- ...
Page 98
... Page 98 Row Row 0 Row 1 Row 2 Row 7 Row 8 Row 14 Row 15 Note Lines = 1: lines in the character bitmap Lines = 2: lines in the character bitmap S1D13700F01 X42A-A-002- Line Figure 13-1 Row Select Address ≤ ...
Page 99
... Write ROW 1 data P3 88h Write ROW 2 data P4 88h Write ROW 3 data P5 F8h Write ROW 4 data P6 88h Write ROW 5 data P7 88h Write ROW 6 data P8 00h Write ROW 7 data P9 00h Write ROW 8 data ↓ ↓ ↓ 00h Write ROW 15 data Revision 4.05 Page 99 S1D13700F01 X42A-A-002-04 ...
Page 100
... The following figure shows the character codes and the codes allocated to CGRAM. All codes can be used by the CGRAM if not using the internal ROM, but the CGRAM address must be set to 0. Note If either of CGRAM1 or CGRAM2 are used, only 1 bpp is supported. Lower 4 bits S1D13700F01 X42A-A-002-04 Upper 4 bits ...
Page 101
... Display data and cursor address read 0 1 Display data and parameter write 0 1 Command write Table 14-3 MC68K Family Interface Signals Function 1 0 Display data and cursor address read 0 0 Display data and parameter write 0 0 Command write Revision 4.05 Page 101 S1D13700F01 X42A-A-002-04 ...
Page 102
... A = [TC/R] - [C/ RNDDN([C/R] x [FX] ÷ RNDUP(B ÷ 16 ÷ [FX ÷ For 1 Bpp and [FX] < 8: S1D13700F01 X42A-A-002-04 and f FR Revision 4.05 Epson Research and Development Vancouver Design Center , and lines per frame [L/F] will also ...
Page 103
... For 4 Bpp [ClockDiv] x Ffr x [L/ (Hz) SYSCLK where A = [TC/R] - [C/ RNDDN([C/R] x [FX] ÷ 16 RNDUP(B ÷ 16) For all cases above where: Hardware Functional Specification Issue Date: 2005/12/13 ClockDiv Ffr Frame Rate Revision 4.05 Page 103 S1D13700F01 X42A-A-002-04 ...
Page 104
... Note 1 The remaining pixels on the right-hand side of the display are automatically blanked by the S1D13700F01. There is no need to zero the display memory corresponding to these pixels. 2 Assumes a frame frequency of 70 Hz, 1 bpp, and a clock divide of 4. S1D13700F01 X42A-A-002-04 ...
Page 105
... Epson Research and Development Vancouver Design Center 15.1.2 Initialization Example The initialization example shown below is for a S1D13700F01 with an 8-bit micropro- cessor interface bus and an Epson EG4810S-AR display unit (512 × 128 pixels). Indirect Addressing Note Set the cursor address to the start of each screen’s layer memory, and use MWRITE to fill the memory with space characters, 20h (text screen only) or 00h (graphics screen only). Determining which memory to clear is explained in Section 15.1.3, “ ...
Page 106
... HDOT SCR C = 5Ah P1 = 00h 6 OVLAY C = 5Bh P1 = 01h S1D13700F01 X42A-A-002-04 Operation FY: Vertical character size = 8 pixels (REG[02h] bits 3-0 C/R: 64 display addresses per line (REG[03h] bits 7-0) TC/R: Total address range per line = 90 (REG[04h] bits 7-0) fOSC = 6.5 MHz, fFR = 70 Hz L/F: 128 display lines (REG[05h] bits 7-0 AP: Virtual screen horizontal size is 128 addresses (REG[06h] bits 7-0, REG[07h] ...
Page 107
... CRX: Horizontal cursor size = 5 pixels (REG[15h] bits 3-0) CRY: Vertical cursor size = 7 pixels (REG[16h] bits 3-0) CM: Block cursor (REG[16h] bit 7) Display ON Display Set cursor shift direction to right (REG[17h] bits 1-0) ‘ ’ ‘E’ ‘P’ ‘S’ Revision 4.05 Page 107 S1D13700F01 X42A-A-002-04 ...
Page 108
... P2 = 10h 19 MWRITE C = 42h P1 = FFh ↓ FFh 20 CSRW S1D13700F01 X42A-A-002-04 Operation ‘O’ ‘N’ EPSON Set cursor to start of second screen block (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) Set cursor shift direction to down (REG[17h] bits 1-0) Fill in a square to the left of the ‘E’ ...
Page 109
... Set cursor shift direction to right (REG[17h] bits 1-0) ‘D’ ‘o’ ‘t’ ‘ ’ ‘M’ ‘a’ ‘t’ ‘r’ ‘i’ ‘x’ ‘ ’ ‘L’ ‘C’ ‘D’ Inverse display EPSON Dot matrix LCD Revision 4.05 Page 109 S1D13700F01 X42A-A-002-04 ...
Page 110
... First layer (text): 320 ÷ characters per line, 200 ÷ lines. Required memory size = 40 × 1000 bytes. • Second layer (graphics): 320 ÷ characters per line, 200 ÷ 200 lines. Required memory size = 40 × 200 = 8000 bytes. S1D13700F01 X42A-A-002-04 03E8h 2nd graphics layer ...
Page 111
... X = Don’t care Hardware Functional Specification Issue Date: 2005/12/13 TC/R calculation fOSC = 6 MHz (refer to Section 15.1.1, “SYSTEM SET Command and Parameters” on page 102) fFR = 70 Hz (refer to Section 15.1.1, “SYSTEM SET Command and Parameters” on page 102) [TC/R] = 52, so TC/R = 34h Revision 4.05 Page 111 S1D13700F01 X42A-A-002-04 ...
Page 112
... First layer (graphics): 320 ÷ characters per line, 200 ÷ 200 lines. Required memory size = 40 × 200 = 8000 bytes. • Second layer (graphics): 320 ÷ characters per line, 200 ÷ 200 lines. Required memory size = 8000 bytes. S1D13700F01 X42A-A-002-04 1F40h 2nd graphics layer ...
Page 113
... X = Don’t care Hardware Functional Specification Issue Date: 2005/12/13 TC/R calculation MHz (refer to Section 15.1.1, “SYSTEM SET OSC Command and Parameters” on page 102 (refer to Section 15.1.1, “SYSTEM SET FR Command and Parameters” on page 102) [TC/R] = 52, so TC/R = 34h Revision 4.05 Page 113 S1D13700F01 X42A-A-002-04 ...
Page 114
... Display memory allocation • All layers (graphics): 320 ÷ characters per line, 200 ÷ 200 lines. Required memory size = 40 × 200 = 8000 bytes. 0000h 1st graphics layer (8000 bytes) S1D13700F01 X42A-A-002-04 3E80h 3rd graphics layer (8000 bytes) 1F40h 2nd graphics layer ...
Page 115
... X = Don’t care Hardware Functional Specification Issue Date: 2005/12/13 TC/R calculation MHz (refer to Section 15.1.1, “SYSTEM SET OSC Command and Parameters” on page 102 (refer to Section 15.1.1, “SYSTEM SET FR Command and Parameters” on page 102) [TC/R] = 52, so TC/R = 34h Revision 4.05 Page 115 S1D13700F01 X42A-A-002-04 ...
Page 116
... Smooth Horizontal Scrolling The S1D13700F01 supports smooth horizontal scrolling to the left as shown in Figure 15-5 “HDOT SCR Example,” on page 117. When scrolling left, the screen is effectively moving to the right over the larger virtual screen. ...
Page 117
... The response time of LCD panels changes considerably at low temperatures. Smooth scrolling under these conditions may make the display difficult to read. Hardware Functional Specification Issue Date: 2005/12/13 SAD SAD + 1 SAD + 2 Magnified Visible Figure 15-5 HDOT SCR Example Revision 4.05 Page 117 AP Display C/R Virtual screen S1D13700F01 X42A-A-002-04 ...
Page 118
... Page 118 15.4 Layered Display Attributes S1D13700F01 incorporates a number of functions for enhancing displays using monochrome LCD panels. It allows the display of inverse characters, half-intensity menu pads and flashing of selected screen areas. These functions are controlled by REG[18h] Overlay Register and REG[0Ah] Display Attribute Register. ...
Page 119
... REG[18h] Overlay Register = 00h 2. REG[0Ah] Display Attribute Register = 34h Hardware Functional Specification Issue Date: 2005/12/13 SAD2 + 2nd layer Revision 4.05 Page 119 Half-tone AB Combined layer display S1D13700F01 X42A-A-002-04 ...
Page 120
... Divide both layer 1 and layer 2 into two screen blocks each, layer 2 being divided into the area to be flashed and the remainder of the screen. Flash the layer 2 screen block for the area to be flashed and combine the layers using the OR function. ABC S1D13700F01 X42A-A-002-04 XYZ Figure 15-8 Flash Attribute for a Large Area Revision 4 ...
Page 121
... To write large characters, use the following procedure. For further information, see the flowchart in Figure 15-9 “Graphics Address Indexing,” on page 122. 1. Reads the character data from the CGRAM 2. Set the display address 3. Writes to the display memory Hardware Functional Specification Issue Date: 2005/12/13 Revision 4.05 Page 121 S1D13700F01 X42A-A-002-04 ...
Page 122
... Data written into the S1D13700F01 display memory Figure 15-9 Graphics Address Indexing Revision 4.05 Epson Research and Development Vancouver Design Center CGROM output (n) shows the CG data readout order (Kanji pattern) (4) (2) (3) (1) Hardware Functional Specification ...
Page 123
... If CGRAM is also used, 96 fixed characters and 32 bank- switchable characters are also be supported. Hardware Functional Specification Issue Date: 2005/12/13 (2) (4) (6) 240 dots (8) (10) (12) (14) (16) (18) (20) (22) (24) (26) (28) (30) (32) Figure 15-10 Graphics Bit Map Revision 4.05 Page 123 320 dots S1D13700F01 X42A-A-002-04 ...
Page 124
... Page 124 For Direct Addressing Mode For Indirect Addressing Mode S1D13700F01 X42A-A-002-04 Start Enable cursor downwards movement Set column 1 cursor address Write data Set column 2 cursor address Write data End Start Enable cursor downwards movement Set column 1 cursor address Write data ...
Page 125
... D 1 Note The shaded positions indicate characters that have the whole 6 × 8 bitmap blackened. Hardware Functional Specification Issue Date: 2005/12/13 Character code bits Figure 16-1 On-Chip Character Set Revision 4.05 Page 125 S1D13700F01 X42A-A-002-04 ...
Page 126
... The S1D13700F01 is removed from power save mode by writing a 0 the Power Save Mode Enable bit, REG[08h] bit 0. However, after disabling power save mode, one dummy write to any register must be performed for direct addressing mode, and at least two dummy writes must be performed for indirect addressing mode ...
Page 127
... θ Figure 18-1 Mechanical Drawing TQFP13 - 64 pin Hardware Functional Specification Issue Date: 2005/12/ INDEX Dimension in Millimeters Min Nom - 10 0.1 - 1.0 - 0.5 0.17 - 0.09 - 0° 1.0 - 12 Revision 4.05 Page 127 Max - - 1 0.27 0.2 10° 0. All dimensions in mm 0.08 S1D13700F01 X42A-A-002-04 ...
Page 128
... Page 128 19 References The following documents contain additional information related to the S1D13700F01. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. • S1D13700 Product Brief (X42A-A-002-xx) S1D13700F01 X42A-A-002-04 Epson Research and Development Revision 4 ...
Page 129
... Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk// 20.2 Ordering Information To order the S1D13700F01 LCD Controller, contact the Epson sales representative in your area. Hardware Functional Specification Issue Date: 2005/12/13 North America Epson Electronics America, Inc. 150 River Oaks Parkway ...
Page 130
... DB[7:0] state during display off changed to “—” XCD1 pin changed to “XCD1 / XCG1” XCD1 / XCG1 state during display off changed to “Running” XCD1 / XCG1 state during power save mode changed to “Stopped” S1D13700F01 X42A-A-002-04 Change Record Revision 4.05 Epson Research and Development ...
Page 131
... S1D13700F01 and the display when indirect addressing is used.” to “The SYSTEM SET command is used to configure the S1D13700F01 for the display used and to exit power save mode when indirect addressing is used.” • section 10.3.1, in the Power Save Registers section, changed “'standby mode” to “power save mode” ...
Page 132
... SYSTEM SET command.” • section 11.1.1, in the SYSTEM SET section, added the following note “If the S1D13700F01 is in power save mode (at power up or after a POWER SAVE command), the SYSTEM SET command will exit power save mode. After writing the SYSTEM SET command and its 8 parameters, the S1D13700F01 will be in normal operation.” ...
Page 133
... CGRAM is used • section 13.3, added note about 1bpp only when CGRAM is used • section 15.1.1, updated TC/R’ formulas for 1 Bpp and 2 Bpp • section 19, added reference to the Product Brief Hardware Functional Specification Issue Date: 2005/12/13 Revision 4.05 Page 133 S1D13700F01 X42A-A-002-04 ...