S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet

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S1D13705

Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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S1D13705 Embedded Memory LCD Controller
S1D13705
TECHNICAL MANUAL
Document No. X27A-Q-001-04
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

Related parts for S1D13705

S1D13705 Summary of contents

Page 1

... S1D13705 Embedded Memory LCD Controller S1D13705 TECHNICAL MANUAL Document No. X27A-Q-001-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice.You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...

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... Page 2 S1D13705 X27A-Q-001-04 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 01/04/18 ...

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... Fax: 089-14005-110 Page 3 Taiwan Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 S1D13705 X27A-Q-001-04 ...

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... Page 4 S1D13705 X27A-Q-001-04 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 01/04/18 ...

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... S1D13705 Embedded Memory LCD Controller The S1D13705 is a color/monochrome LCD graphics controller with an embedded 80K Byte SRAM display buffer. The high integration of the S1D13705 provides a low cost, low power, single chip solution to meet the requirements of embedded markets such as Office Automation equipment, Mobile Commu- nications devices, and Palm-size PCs where board size and battery life are major concerns. Products requiring a “ ...

Page 6

... Clock Source • Single clock input for both pixel and memory clocks. • The S1D13705 clock source can be internally divided down for a higher frequency clock input. • Dynamic switching of memory clocks in portrait mode. CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS: • ...

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... S1D13705 Embedded Memory LCD Controller Hardware Functional Specification Document Number: X27A-A-001-09 Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice.You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...

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... Page 2 S1D13705 X27A-A-001-09 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/05/22 ...

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... Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . 22 5.4 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 Bus Interface Timing 7.1.1 SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.2 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.3 Motorola MC68K #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1.4 Motorola MC68K #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 31 Hardware Functional Specification Issue Date: 01/05/22 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . Page 3 S1D13705 X27A-A-001-09 ...

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... Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.1 Software Power Save Mode 13.2 Hardware Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . .81 13.3 Power Save Mode Function Summary 13.4 Panel Power Up/Down Sequence 13.5 Turning Off BCLK Between Accesses . . . . . . . . . . . . . . . . . . . . . 83 13.6 Clock Requirements 14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 S1D13705 X27A-A-001- .84 Epson Research and Development Vancouver Design Center ...

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... Table 12-1: Default and Alternate SwivelView Mode Comparison . . . . . . . . . . . . . . . . . . 80 Table 13-1: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 13-2: Software Power Save Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 13-3: Hardware Power Save Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 13-4: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 13-5: S1D13705 Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Hardware Functional Specification Issue Date: 01/05/22 List of Tables Page 5 ...

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... Page 6 S1D13705 X27A-A-001-09 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/05/22 ...

Page 13

... Figure 7-24: 12-Bit TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 7-25: TFT/D-TFD A.C. Timing Figure 8-1: Screen-Register Relationship, Split Screen Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . . 70 Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . . 70 Hardware Functional Specification Issue Date: 01/05/22 List of Figures Page 7 S1D13705 X27A-A-001-09 ...

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... Figure 11-6: 4 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 11-7: 8 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 12-1: Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Default Mode . . . . . . . . . . . . . . . . . 76 Figure 12-2: Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Alternate Mode . . . . . . . . . . . . . . . . 78 Figure 13-1: Panel On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 14-1: Mechanical Drawing QFP14 ...

Page 15

... Products requiring a “Portrait” display can take advantage of the SwivelView™ Mode feature of the S1D13705. Virtual and Split Screen are just some of the display modes supported. The above features, combined with the Operating System independence of the S1D13705, make it the ideal solution for a wide variety of applications ...

Page 16

... Register level support for EL panels. • Example resolutions: 640x480 at a color depth of 2 bpp 640x240 at a color depth of 4 bpp 320x240 at a color depth of 8 bpp S1D13705 X27A-A-001-09 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/05/22 ...

Page 17

... GPIO[4:1] are available if upper LCD data pins (FPDAT[11:8]) are not required for TFT/D-TFD support or hardware inverse video. • Core operates from 2.7 volts to 3.6 volts. • IO Operates from the core voltage up to 5.5 volts. 2.7 Package • 80 pin QFP14 package. Hardware Functional Specification Issue Date: 01/05/22 CLK = CLKI or CLK = CLKI/2 Page 11 S1D13705 X27A-A-001-09 ...

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... Figure 3-2: Typical System Diagram (SH-3 Bus) S1D13705 X27A-A-001-09 . Oscillator CS# AB[16:0] DB[15:0] WE1# S1D13705 BS# RD/WR# RD# WE0# WAIT# BCLK RESET# . Oscillator CS# AB[16:0] DB[15:0] WE1# S1D13705 BS# RD/WR# RD# WE0# WAIT# BCLK RESET# Epson Research and Development Vancouver Design Center FPDAT[7:0] D[7:0] FPSHIFT FPSHIFT 8-bit FPFRAME FPFRAME LCD FPLINE FPLINE Display DRDY MOD ...

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... WAIT# BCLK RESET# . Oscillator CS# AB[16:0] DB[15:0] FPDAT[7:0] WE1# S1D13705 BS# RD/WR# RD# WE0# WAIT# BCLK RESET# Page 13 FPDAT[7:4] D[3:0] FPSHIFT FPSHIFT 4-bit FPFRAME FPFRAME LCD FPLINE FPLINE Display DRDY MOD LCDPWR D[7:0] FPSHIFT FPSHIFT 8-bit FPFRAME FPFRAME LCD FPLINE FPLINE Display DRDY MOD LCDPWR S1D13705 X27A-A-001-09 ...

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... S1D13705 X27A-A-001-09 . Oscillator BS# CS# AB[16:0] DB[15:0] FPDAT[11:0] S1D13705 WE0# WE1# RD RD/WR# WAIT# BCLK RESET# . Oscillator BS# CS# AB[16:0] DB[15:0] WE0# S1D13705 RD# WE1# WAIT# BCLK RESET# Epson Research and Development Vancouver Design Center D[11:0] FPSHIFT FPSHIFT 12-bit FPFRAME FPFRAME TFT FPLINE FPLINE Display DRDY DRDY LCDPWR FPDAT[8:0] D[8:0] FPSHIFT ...

Page 21

... The Sequence Controller controls data flow from the Memory Controller through the Look- Up Table and to the LCD Interface. It also generates memory addresses for display refresh accesses. Hardware Functional Specification Issue Date: 01/05/22 40k x 16-bit SRAM Memory Power Save Controller Clocks Look-Up Table Sequence Controller Memory Clock Pixel Clock Page 15 LCD LCD I/F S1D13705 X27A-A-001-09 ...

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... The LCD Interface performs frame rate modulation for passive LCD panels. It also generates the correct data format and timing control signals for various LCD and TFT/D-TFD panels. 4.1.6 Power Save Power Save contains the power save mode circuitry. S1D13705 X27A-A-001-09 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...

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... Note Package type: 80 pin surface mount QFP14 Hardware Functional Specification Issue Date: 01/05/22 S1D13705 Figure 5-1: Pinout Diagram Page 17 40 VSS 39 FPFRAME 38 FPLINE 37 FPDAT0 36 FPDAT1 35 FPDAT2 34 FPDAT3 33 FPDAT4 32 FPDAT5 31 FPDAT6 30 FPDAT7 29 IOVDD 28 FPSHIFT 27 VSS 26 FPDAT8 25 FPDAT9 24 FPDAT10 23 FPDAT11 22 GPIO0 21 COREVDD S1D13705 X27A-A-001-09 ...

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... AB[16:1] I 63, 64, 65, 66, 67, 68 11, 12, DB[15:0] IO 13, 14, 15, 16, 17, 18, 19 S1D13705 X27A-A-001- Table 6-4: “Output Specifications,” on page 25 RESET# Cell State This pin has multiple functions. • For SH-3/SH-4 mode, this pin inputs system address bit 0 (A0). • ...

Page 25

... This pin has multiple functions. • For SH-3/SH-4 mode, this pin inputs the RD/WR# signal. The S1D13705 needs this signal for early decode of the bus cycle. • For MC68K #1, this pin inputs the R/W# signal. • For MC68K #2, this pin inputs the R/W# signal. ...

Page 26

... IO O, FPDAT11 23 IO FPFRAME O 39 S1D13705 X27A-A-001-09 RESET# Cell State This pin has multiple functions. • For SH-3/SH-4 mode, this pin inputs the read signal (RD#). • For MC68K #1, this pin must be tied • For MC68K #2, this pin inputs the bus size bit 1 (SIZ1). ...

Page 27

... Pin # Driver 51 C Input Clock RESET# Cell State These inputs are used to configure the S1D13705 - see Table As set by 5-1: “Summary of Power On/Reset Options,” on page 22. C hardware Must be connected directly This pin has multiple functions - see REG[03h] bit 2. CS/ Input • ...

Page 28

... Host Bus Interface Pin Mapping S1D13705 SH-3 Pin Names AB[16:1] A[16:1] AB0 A0 DB[15:0] D[15:0] WE1# WE1# CS# CSn# BCLK CKIO BS# BS# RD/WR# RD/WR# RD# RD# WE0# WE0# WAIT# WAIT# RESET# RESET# S1D13705 X27A-A-001-09 Power On/Reset State CNF2 CNF1 CNF0 BS ...

Page 29

... LD1 R1 D2 LD2 R0 D3 LD3 G2 D4 UD0 G1 D5 UD1 G0 D6 UD2 B2 D7 UD3 B1 GPIO1 GPIO1 B0 GPIO2 GPIO2 GPIO2 GPIO3 GPIO3 GPIO3 GPIO4/ GPIO4/ Hardware Hardware GPIO4 Video Video Invert Invert . DD X27A-A-001-09 Page 23 12-bit S1D13705 ...

Page 30

... High Level Input Voltage V IH CMOS inputs Positive-going Threshold V T+ CMOS Schmitt inputs Negative-going Threshold V T- CMOS Schmitt inputs I Input Leakage Current IZ C Input Pin Capacitance IN S1D13705 X27A-A-001-09 Table 6-1: Absolute Maximum Ratings V - 0.3 to 4.0 SS Core -65 to 150 260 for 10 sec ...

Page 31

... Type = 5. -0.4V, Type = MAX Page 25 Typ Max Units - S1D13705 X27A-A-001-09 A ...

Page 32

... D[15:0] Hi-Z (write) D[15:0] Hi-Z (read) Note The SH-4 Wait State Control Register for the area in which the S1D13705 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK). S1D13705 X27A-A-001- for all inputs must be < 5 nsec (10% ~ 90%) ...

Page 33

... BCLK Between Accesses” on page 83 Hardware Functional Specification Issue Date: 01/05/22 Table 7-1: SH-4 Timing Parameter CKIO after BS# (write cycle) Page 27 Min Max Units 50 MHz 1/f CKIO 1.5T CKIO T CKIO S1D13705 X27A-A-001-09 ...

Page 34

... CSn# WEn# RD# Hi-Z WAIT# D[15:0] Hi-Z (write) D[15:0] Hi-Z (read) Note The SH-3 Wait State Control Register for the area in which the S1D13705 resides must be set to a non-zero value. S1D13705 X27A-A-001- t13 t12 t14 Figure 7-2: SH-3 Bus Timing Epson Research and Development Vancouver Design Center t5 t11 ...

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... Issue Date: 01/05/22 Table 7-2: SH-3 Bus Timing Parameter CKIO after BS# (write cycle) One Software WAIT State Required Page 29 a Min Max Units 50 MHz 1/f CKIO 1.5T CKIO S1D13705 X27A-A-001-09 ...

Page 36

... UDS#, LDS# falling edge to D[15:0] driven (read cycle) t11 D[15:0] valid to DTACK# falling edge (read cycle) t12 UDS#, LDS# rising edge to D[15:0] high impedance Note CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 83 S1D13705 X27A-A-001-09 VALID t11 ...

Page 37

... Issue Date: 01/05/22 VALID t10 VALID Figure 7-4: MC68K #2 Timing (MC68030) Table 7-4: MC68K #2 Timing (MC68030) Parameter Hi-Z t9 Hi-Z VALID t11 Hi-Z Min Max Units 33 MHz 1/f CLK CLK CLK T /2 CLK S1D13705 X27A-A-001-09 Page 31 ...

Page 38

... WAIT# high impedance t11 WAIT# high to WE0#, WE1#, RD0#, RD1# high Note BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 83 S1D13705 X27A-A-001-09 VALID Figure 7-5: Generic #1 Timing Table 7-5: Generic #1 Timing ...

Page 39

... BCLK Between Accesses” on page 83 Hardware Functional Specification Issue Date: 01/05/22 VALID Figure 7-6: Generic #2 Timing Table 7-6: Generic #2 Timing Parameter t2 t4 VALID t7 t6 VALID t10 t11 Min Max Units 50 1/f BCLK BCLK BCLK X27A-A-001-09 Page 33 Hi-Z Hi-Z MHz S1D13705 ...

Page 40

... Input Clock Pulse Width Low (CLKI) PWL t Input Clock Fall Time (10 Input Clock Rise Time (10% - 90%) r Note When CLKI is > 25MHz it must be divided by 2 (REG[02h] bit 4 = 1). S1D13705 X27A-A-001- PWH PWL CLKI Figure 7-7: Clock Input Requirements ...

Page 41

... FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active to t2 LCDPWR Note Where T Hardware Functional Specification Issue Date: 01/05/ Table 7-8: LCD Panel Power On/Reset Timing Parameter is the period of FPFRAME and T FPFRAME 11 ACTIVE t2 Min Typ Max T FPFRAME 0 is the period of the pixel clock. PCLK X27A-A-001-09 Page 35 Units ns Frames S1D13705 ...

Page 42

... LCDPWR Override = 0 HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY, t5 LCDPWR active - LCDPWR Override = 0 t6 LCDPWR Override active (1) to LCDPWR inactive t7 LCDPWR Override inactive (1) to LCDPWR active S1D13705 X27A-A-001- Inactive Active t4 t5 Figure 7-9: Power Down/Up Timing Table 7-9: Power Down/Up Timing ...

Page 43

... Horizontal Non-Display Period Hardware Functional Specification Issue Date: 01/05/22 VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 HDP 1-1 1-5 1-2 1-6 1-3 1-7 1-4 1-8 = (REG[06h] bits 1-0, REG[05h] bits 7- Lines = REG[0Ah] bits 5-0 Lines = ((REG[04h] bits 6- 8Ts = (REG[08h 8Ts Page 37 VNDP LINE1 LINE2 HNDP 1-317 1-318 1-319 1-320 S1D13705 X27A-A-001-09 ...

Page 44

... S1D13705 X27A-A-001- t14 t7 Parameter Epson Research and Development Vancouver Design Center ...

Page 45

... Issue Date: 01/05/22 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-1 1-9 1-2 1-10 1-3 1-11 1-4 1-12 1-5 1-13 1-6 1-14 1-7 1-15 1-8 1-16 = (REG[06h] bits 1-0, REG[05h] bits 7- Lines = REG[0Ah] bits 5-0 Lines = ((REG[04h] bits 6- 8Ts = (REG[08h 8Ts Page 39 VNDP LINE1 LINE2 HNDP 1-633 1-634 1-635 1-636 1-637 1-638 1-639 1-640 S1D13705 X27A-A-001-09 ...

Page 46

... Ts = pixel clock period 9Ts min min [((REG[04h] bits 6-0)+ ((REG[08h] bits 4- 8]Ts min [(REG[08h] bits 4- 4]Ts min 5. t7 =[(REG[08h] bits 4- 13]Ts min S1D13705 X27A-A-001-09 Epson Research and Development t14 t11 t7 t12 t13 1 Min ...

Page 47

... VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 HDP 1-G2 1-B3 1-B2 1-R4 1-R3 1-G4 1-G3 1-B4 Figure 7-14: Single Color 4-Bit Panel Timing = (REG[06h] bits 1-0, REG[05h] bits 7- Lines = REG[0Ah] bits 5-0 Lines = ((REG[04h] bits 6- 8Ts = (REG[08h 8Ts Page 41 VNDP LINE1 LINE2 HNDP 1-B319 1-R320 1-G320 1-B320 S1D13705 X27A-A-001-09 ...

Page 48

... S1D13705 X27A-A-001- t14 t7 Parameter Epson Research and Development Vancouver Design Center t11 ...

Page 49

... REG[05h] bits 7- Lines = REG[0Ah] bits 5-0 Lines = ((REG[04h] bits 6- 8Ts = (REG[08h 8Ts Page 43 VNDP LINE1 LINE2 HNDP 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640 S1D13705 X27A-A-001-09 ...

Page 50

... S1D13705 X27A-A-001- t6a t6b t14 t7a t7b t12 t13 Parameter Epson Research and Development Vancouver Design Center t2 ...

Page 51

... Issue Date: 01/05/22 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-B3 1-G6 1-R4 1-B6 1-G4 1-R7 1-B4 1-G7 1-R5 1-B7 1-G5 1-R8 1-B5 1-G8 1-R6 1-B8 = (REG[06h] bits 1-0, REG[05h] bits 7- Lines = REG[0Ah] bits 5-0 Lines = ((REG[04h] bits 6- 8Ts = (REG[08h 8Ts Page 45 VNDP LINE1 LINE2 HNDP 1-G638 1-B638 1-R639 1-G639 1-B639 1-R640 1-G640 1-B640 S1D13705 X27A-A-001-09 ...

Page 52

... S1D13705 X27A-A-001- t14 Parameter Epson Research and Development Vancouver Design Center ...

Page 53

... REG[05h] bits 7- Lines = REG[0Ah] bits 5-0 Lines = ((REG[04h] bits 6- 8Ts = (REG[08h 8Ts Page 47 VNDP LINE 1/241 LINE 2/242 HNDP 1-637 1-638 1-639 1-640 241-637 241-638 241-639 241-640 S1D13705 X27A-A-001-09 ...

Page 54

... S1D13705 X27A-A-001- t14 Parameter Epson Research and Development Vancouver Design Center ...

Page 55

... Figure 7-22: Dual Color 8-Bit Panel Timing = (REG[06h] bits 1-0, REG[05h] bits 7- Lines = REG[0Ah] bits 5-0 Lines = ((REG[04h] bits 6- 8Ts = (REG[08h 8Ts VNDP LINE 239/479 LINE 240/480 LINE 1/241 HNDP 1-B639 1-R640 1-G640 1-B640 2 41- B639 241- R640 241- G640 241- B640 X27A-A-001-09 Page 49 S1D13705 ...

Page 56

... S1D13705 X27A-A-001- t14 Parameter Epson Research and Development Vancouver Design Center ...

Page 57

... VNDP1 + VNDP2 = (REG[0Ah] bits 5-0) Lines = REG[09h] bits 5-0 Lines = (REG[0Ah] bits 5-0) - (REG[09Ah] bits 5-0) Lines = ((REG[04h] bits 6- 8Ts = HNDP1 + HNDP2 = (REG[08h 8Ts = ((REG[07h] bits4- +16Ts = (((REG[08h] bits4-0) - (REG[07h] bits 4-0 +16Ts VDP VNDP 1 LINE1 LINE480 HDP HNDP 1 1-640 1-640 1-640 Page 51 S1D13705 X27A-A-001-09 ...

Page 58

... Page 52 Frame Pulse Line Pulse Line Pulse DRDY Shift Pulse FPDAT[11:0] Note: DRDY is used to indicate the first pixel S1D13705 X27A-A-001-09 t9 t12 t7 t17 t11 Figure 7-25: TFT/D-TFD A.C. Timing Epson Research and Development Vancouver Design Center t8 t6 t14 t13 t16 t4 t5 ...

Page 59

... Ts 7. t17min = [(REG[08h] bits 4-0) - (REG[07 16] Ts Hardware Functional Specification Issue Date: 01/05/22 Table 7-17: TFT/D-TFD A.C. Timing Parameter Min 1 0.5 0.5 0.5 0.5 note 2 9 note 3 2t6 note 4 0 18Ts 0.5 note 5 note 6 0.5 note 7 Page 53 Typ Max Units (note 250 S1D13705 X27A-A-001-09 ...

Page 60

... Page 54 8 Registers 8.1 Register Mapping The S1D13705 registers are located in the upper 32 bytes of the 128K byte S1D13705 address range. The registers are accessible when CS and AB[16:0] are in the range 1FFE0h through 1FFFFh. 8.2 Register Descriptions Unless specified otherwise, all register bits are reset to 0 during power up. ...

Page 61

... Mono Single 4-bit passive LCD Mono Single 8-bit passive LCD reserved reserved reserved Mono Dual 8-bit passive LCD reserved reserved Color Single 4-bit passive LCD reserved reserved Color Dual 8-bit passive LCD reserved reserved 9-bit TFT/D-TFD panel 12-bit TFT/D-TFD panel S1D13705 X27A-A-001-09 ...

Page 62

... This bit can be set to 1 just before a major screen update, then set back save power after the update. This bit has no effect in Swivel- View mode. Refer to REG[1Bh] SwivelView Mode Register on page 66 for SwivelView mode clock selection. S1D13705 X27A-A-001-09 Input Clock High ...

Page 63

... Video data is inverted after the Look-Up Table. Hardware Video Invert Enable Hardware Functional Specification Issue Date: 01/05/22 Table 8-4: Inverse Video Mode Select Options Software Video Invert (Passive and Active Panels FPDAT11 Video Data (Passive Panels Only) X Normal X Inverse 0 Normal 1 Inverse X27A-A-001-09 Page 57 S1D13705 ...

Page 64

... These bits select the Power Save Mode as shown in the following table. Table 8-6: Software Power Save Mode Selection Bit Refer to Section 13, “Power Save Modes” on page 81 for a complete description of the power save modes. S1D13705 X27A-A-001-09 LCDPWR n/a n/a Override Table 8-5: Hardware Power Save/GPIO0 Operation Hardware Power GPIO0 Config ...

Page 65

... Horizontal Panel Size Bit Panel Size Bit Panel Size Bit 2 1 – Read/Write Vertical Panel Vertical Panel Vertical Panel Size Size Bit 2 Bit 1 Read/Write Vertical Panel Vertical Panel n/a Size Bit 9 – 1 X27A-A-001-09 Page 59 0 Size Bit 0 Size Bit 8 S1D13705 ...

Page 66

... FPFRAME. This register is effective in TFT/D-TFD mode only (REG[01h] bit 7 = 1). This register is programmed as follows: The contents of this register must be greater than zero and less than or equal to the Vertical Non-Display Period Register, i.e. S1D13705 X27A-A-001-09 FPLINE Start FPLINE Start ...

Page 67

... Period Bit 3 = REG[0Ah] bits [5:0] MOD Rate MOD Rate Bit 5 Bit 4 Bit 3 Read/Write Vertical Non- Vertical Non- Vertical Non- Display Display Display Period Bit 2 Period Bit 1 Period Bit 0 Read/Write MOD Rate MOD Rate MOD Rate Bit 2 Bit 1 Bit 0 S1D13705 X27A-A-001-09 Page 61 ...

Page 68

... REG[10h] Screen Start Address Overflow Register Address = 1FFF0h n/a n/a bit 0 Screen 1 Start Address Bit 16 This bit is the most significant bit of Screen 1 Start Address for SwivelView mode. This bit has no effect in Landscape mode. S1D13705 X27A-A-001-09 Screen 1 Start Screen 1 Start Address Address Bit 5 Bit 4 ...

Page 69

... REG[13h] bits 1-0 Screen 1 Vertical Size Bits [9:0] REG[12h] bits 7-0 This register is used to implement the Split Screen feature of the S1D13705. These bits determine the height (in lines) of Screen 1. In landscape modes, if this register is programmed with a value, n, where n is less than the Vertical Panel Size (REG[06h], REG[05h]), then lines the panel contain Screen 1 and lines n+1 to REG[06h], REG[05h] of the panel contain Screen 2. See Figure 8-1: “ ...

Page 70

... Bit 6 bits 7-0 LUT Address Bits [7:0] These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13705 has three 256-position, 4-bit wide LUTs, one for each of red, green, and blue – refer to Section 11, “Look-Up Table Architecture” on page 70 for details. This register selects which LUT entry is read/write accessible through the LUT Data Reg- ister (REG[17h]) ...

Page 71

... FPDAT[11:8] for TFT/D-TFD operation). When configured as IO, all unused pins must be tied Hardware Functional Specification Issue Date: 01/05/22 LUT Data n/a Bit 1 Bit 0 GPIO4 Pin IO GPIO3 Pin IO n/a Configuration Configuration Read/Write n/a n/a n/a Read/Write GPIO2 Pin IO GPIO1 Pin IO GPIO0 Pin IO Configuration Configuration Configuration . DD S1D13705 X27A-A-001-09 Page 65 ...

Page 72

... SwivelView Mode Select When this bit = 0, Default SwivelView Mode is selected. When this bit = 1, Alternate SwivelView Mode is selected. See Section 12, “SwivelView™” on page 76 for further information on SwivelView Mode. The following table shows the selection of SwivelView Mode. S1D13705 X27A-A-001-09 GPIO4 Pin IO GPIO3 Pin IO n/a ...

Page 73

... When the Line Byte Count Register = n, where 1 n REG[1Eh] and REG[1Fh] REG[1Eh] and REG[1Fh] are reserved for factory S1D13705 testing and should not be written. Any value written to these registers may result in damage to the S1D13705 and/or any panel connected to the S1D13705. Hardware Functional Specification ...

Page 74

... The following formulae are used to calculate the display frame rate. TFT/D-TFD and Passive Single-Panel modes Where: f HDP HNDP = Horizontal Non-Display Period = ((REG[08h] bits 4- Pixels VDP VNDP = Vertical Non-Display Period = (REG[0Ah] bits 5-0) Lines Passive Dual-Panel mode Where: S1D13705 X27A-A-001-09 f PCLK FrameRate = ---------------------------------------------------------------------------------------- - HDP + ...

Page 75

... Panel Display Panel Display Panel Display S1D13705 X27A-A-001-09 ...

Page 76

... Green Look-Up Table 256x4 bit-per-pixel data from Display Buffer Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path S1D13705 X27A-A-001-09 Epson Research and Development 4-bit Gray Data unused Look-Up Table entries 00 4-bit Gray Data unused Look-Up Table entries ...

Page 77

... Display Buffer Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path Hardware Functional Specification Issue Date: 01/05/22 0000 0001 0010 0011 0100 0101 0110 4-bit Gray Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 = unused Look-Up Table entries Page 71 S1D13705 X27A-A-001-09 ...

Page 78

... FF Blue Look-Up Table 256x4 bit-per-pixel data from Display Buffer Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path S1D13705 X27A-A-001-09 Epson Research and Development 4-bit Red Data 0 1 4-bit Green Data 0 1 4-bit Blue Data unused Look-Up Table entries ...

Page 79

... bit-per-pixel data from Display Buffer Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path Hardware Functional Specification Issue Date: 01/05/22 00 4-bit Red Data 4-bit Green Data 4-bit Blue Data unused Look-Up Table entries Page 73 S1D13705 X27A-A-001-09 ...

Page 80

... bit-per-pixel data from Display Buffer Figure 11-6: 4 Bit-per-pixel Color Mode Data Output Path S1D13705 X27A-A-001-09 Epson Research and Development 0000 0001 0010 0011 0100 0101 0110 4-bit Red Data 0111 1000 1001 1010 1011 ...

Page 81

... Blue Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 Page 75 S1D13705 X27A-A-001-09 ...

Page 82

... A SwivelView window C 240 image seen by programmer = image in display buffer Figure 12-1: Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Default Mode S1D13705 X27A-A-001-09 80K bytes consumes less power than the Alternate E B display start address D ...

Page 83

... Note Vertical panning by a single line is not supported in Default SwivelView Mode. Hardware Functional Specification Issue Date: 01/05/22 = AddressOfPixelB = AddressOfPixelA = AddressOfPixelA = AddressOfPixelA 256 256 = -------- - = 256 = 00h 8bpb 8bpp 1 + ByteOffset 240pixels 8bpp -------------------------------------------- + – 1 8bpb + EFh :see REG[1Ch] for explanat X27A-A-001-09 Page 77 S1D13705 ...

Page 84

... A SwivelView window C 320 image seen by programmer = image in display buffer Figure 12-2: Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Alternate Mode S1D13705 X27A-A-001-09 B display start address D Epson Research and Development Vancouver Design Center 2 x PCLK. This makes the power ...

Page 85

... Increment the register by the value in the Line Byte Count register to pan vertically by one line, e.g. add A0h to pan by one line in the example above Hardware Functional Specification Issue Date: 01/05/22 = AddressOfPixelB = AddressOfPixelA = AddressOfPixelA = AddressOfPixelA 320 320 REG 1Ch = ----------------------------------------- - = -------- - 8bpb 4bpp 2 + ByteOffset 320pixels 4bpp -------------------------------------------- + – 1 8bpb + 9Fh = 160 = A0h X27A-A-001-09 Page 79 S1D13705 ...

Page 86

... Lowest power consumption. Panning Vertical panning in 2 line increments. Performance Nominal performance. 12.4 SwivelView Mode Limitations The only limitation to using SwivelView mode on the S1D13705 is that split screen operation is not supported. S1D13705 X27A-A-001-09 Default SwivelView Mode Epson Research and Development Vancouver Design Center Alternate SwivelView Mode Does not require a virtual image ...

Page 87

... Epson Research and Development Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the S1D13705 to accommodate the need for power reduction in the hand-held devices market. These modes are enabled as follows: Hardware Power Save Not Configured or 0 Not Configured or 0 ...

Page 88

... Panel Power Up/Down Sequence After chip reset or when entering/exiting a power save mode, the Panel Interface signals follow a power on/off sequence shown below. This sequence is essential to prevent damage to the LCD panel. S1D13705 X27A-A-001-09 Table 13-4: Power Save Mode Function Summary IO Access Possible? ...

Page 89

... BCLK must be present for at least one T Hardware Functional Specification Issue Date: 01/05/ frame 127 frames power-up power-down Figure 13-1: Panel On/Off Sequence BCLK 00 11 Power Save Mode 0 frame power-up + 12T ] after the end of the BCLK MCLK before the start of an access. S1D13705 X27A-A-001-09 Page 83 ...

Page 90

... Page 84 13.6 Clock Requirements The following table shows what clock is required for which function in the S1D13705 Table 13-5: S1D13705 Internal Clock Requirements Function Is required during register accesses. BCLK can be shut down between accesses: allow eight BCLK pulses plus 12 MCLK pulses Register Read/Write (8T before shutting BCLK off. Allow one BCLK ...

Page 91

... Epson Research and Development Vancouver Design Center 14 Mechanical Data QFP14 - 80 pin 61 80 Hardware Functional Specification Issue Date: 01/05/22 ± 0.4 14.0 ± 0.1 12.0 60 Index 1 + 0.1 0.18 0.5 - 0.05 Figure 14-1: Mechanical Drawing QFP14 Unit 0~10° ± 0.2 0.5 1.0 X27A-A-001-09 Page 85 S1D13705 ...

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... Page 86 S1D13705 X27A-A-001-09 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/05/22 ...

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... S1D13705 Embedded Memory LCD Controller Programming Notes and Examples Document Number: X27A-G-002-02 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice.You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...

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... Page 2 S1D13705 X27A-G-002-02 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/13 ...

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... LCD Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 Hardware Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 Introduction To Hardware Rotation . . . . . . . . . . . . . . . . . . . . . . 37 7.2 Default Portrait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 Alternate Portrait Mode 7.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.5 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Programming Notes and Examples Issue Date: 01/02/13 Table of Contents . . . . . . . . . . . . . . . . . . . . Page 3 S1D13705 X27A-G-002-02 ...

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... Porting LIBSE to a new target platform . . . . . . . . . . . . . . . . . . . . .64 9.5.1 Building the LIBSE library for SH3 target example . . . . . . . . . . . . . . . . . 65 9.5.2 Building the HAL library for the target example . . . . . . . . . . . . . . . . . . . 65 10 Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1 Sample code using the S1D13705 HAL API . . . . . . . . . . . . . . . . . . .66 10.2 Sample code without using the S1D13705 HAL API . . . . . . . . . . . . . . . .68 10.3 Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 S1D13705 X27A-G-002- ...

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... Epson Research and Development Vancouver Design Center Table 2-1: S1D13705 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4-1: Recommended LUT Values for 1 Bpp Color Mode . . . . . . . . . . . . . . . . . . . . 17 Table 4-2: Example LUT Values for 2 Bpp Color Mode . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4-3: Suggested LUT Values to Simulate VGA Default 16 Color Palette . . . . . . . . . . . 19 Table 4-4: Suggested LUT Values to Simulate VGA Default 256 Color Palette . . . . . . . . . . . 20 Table 4-5: Recommended LUT Values for 1 Bpp Gray Shade ...

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... Page 6 S1D13705 X27A-G-002-02 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/13 ...

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... Epson Research and Development Vancouver Design Center 1 Introduction This guide demonstrates how to program the S1D13705 Embedded Memory Color LCD Controller. The guide presents the basic concepts of the LCD controller and provides methods to directly program the registers. It explains some of the advanced techniques used and the special features of the S1D13705 ...

Page 100

... Display Buffer Location Before we can perform the initialization we have to know where to find the S1D13705 display memory and control registers. The S1D13705 contains 80 kilobytes of internal display memory. External support logic must be employed to decode the starting address for this display memory in CPU address space ...

Page 101

... System configuration imposes certain non-variable limitations. For instance the width and height of the display panel are fixed as is, typically, the input clock to the S1D13705. From the following formula it is evident that the two variables the programmer can use to adjust frame rate are horizontal and vertical non-display periods ...

Page 102

... CLKI by 2) PCLK /= still can't hit the frame rate - throw an error. if ((VNDP < (VNDP > 0x3F) || (HNDP < 32) || (HNDP > 280)) { sprintf("ERROR: Unable to set the desired frame rate.\n"); exit(1); } S1D13705 X27A-G-002-02 PCLK FrameRate = ---------------------------------------------------------------------------------------- - HDP + HNDP ...

Page 103

... Most passive (STN) panels are tolerant of nearly any combination of HNDP and VNDP values, however panel specifications generally specify only a few lines of vertical non- display period. The S1D13705 is capable of generating a vertical non-display period sixty-three lines. This amount of VNDP is far too great a non-display period and will likely degrade display quality ...

Page 104

... Page 12 3 Memory Models The S1D13705 is capable of operating at four different color depths. For each color depth the data format is packed pixel. S1D13705 packed pixel modes can range from one byte containing eight adjacent pixels (1-bpp) to one byte containing just one pixel (8-bpp). ...

Page 105

... Programming Notes and Examples Issue Date: 01/02/13 Bit 5 Bit 4 Bit 3 Pixel 1 Pixel 2 Bit 1 Bit 0 Bit 1 Bit 5 Bit 4 Bit 3 Pixel 0 Pixel 1 Bit 1 Bit 0 Bit 3 Page 13 Bit 2 Bit 1 Bit 0 Pixel 2 Pixel 3 Pixel 3 Bit 0 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 Pixel 1 Pixel 1 Pixel 1 Bit 2 Bit 1 Bit 0 S1D13705 X27A-G-002-02 ...

Page 106

... Bit 7 Bit 6 Red bit 2 Red bit 1 Red bit 0 Figure 3-4: Pixel Storage for 8 Bpp (256 Colors) in One Byte of Display Buffer S1D13705 X27A-G-002-02 Bit 5 Bit 4 Bit 3 Green bit 2 Green bit 1 Epson Research and Development ...

Page 107

... VGA RAMDAC. However, there are two considerations which must be kept in mind. • The S1D13705 Look-Up Table has four bits (16 levels) of intensity per primary color. The standard VGA RAMDAC has six bits (64 levels). This four to one difference must be taken into consideration when converting from a VGA palette to a LUT palette. One suggestion is to divide the VGA intensity level by four to arrive at the LUT intensity ...

Page 108

... After the third access the LUT Address is incremented by one, then next access to this register will be the red element of the next Look-Up Table index. S1D13705 X27A-G-002-02 LUT Address ...

Page 109

... Look-Up Table Organization 4.2.1 Color Modes 1 bpp color When the S1D13705 is configured for 1 bpp color mode, the LUT is limited to selecting colors from the first two entries. The two LUT entries can be any two RGB values but are typically set to black-and-white. Each byte in the display buffer contains eight adjacent pixels bit has a value of “0” then the color in LUT 0 index is displayed. A bit value of “ ...

Page 110

... Page 18 2 bpp color When the S1D13705 is configured for 2 bpp color mode, the displayed colors are selected from the first four entries of the Look-Up Table. The LUT entries may be set to any of the 4096 possible colors. Each byte in the display buffer contains four adjacent pixels bit combination has a value of “ ...

Page 111

... Epson Research and Development Vancouver Design Center 4 bpp color When the S1D13705 is configured for 4 bpp color mode, the displayed colors are selected from the first sixteen entries of the Look-Up Table. The LUT entries may be set to any of the 4096 possible colors. Each byte in the display buffer contains two adjacent pixels nibble has a value of “ ...

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... Page 20 8 bpp color When the S1D13705 is configured for 8 bpp color mode the entire Look-Up Table is used to display images. Each of the LUT entries may be set to any of the 4096 possible colors. Each byte in the display buffer represents one pixels. The byte value is used directly as an index into one of the 256 LUT entries ...

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... S1D13705 X27A-G-002-02 Page ...

Page 114

... When the S1D13705 is configured for 1 bpp gray shade mode, the LUT is limited to selecting colors from the first two green entries. The two LUT entries can be set to any of sixteen possible intensities. Typically they would be set to 0h (black) and Fh (white). Each byte in the display buffer contains eight adjacent pixels bit has a value of “ ...

Page 115

... The following table shows the example values for 2 bit-per-pixel display mode. Index FF Programming Notes and Examples Issue Date: 01/02/13 Table 4-6: Suggested Values for 2 Bpp Gray Shade Red Green ... indicates unused entries Page 23 Blue S1D13705 X27A-G-002-02 ...

Page 116

... Page 24 4 bpp gray shade When the S1D13705 is configured for 4 bpp gray shade mode the displayed colors are selected from the green values of the first sixteen entries of the Look-Up Table. Each of the sixteen entries can be set to any of the sixteen possible intensity levels. ...

Page 117

... The display panel is 320x240 pixels, an image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling. Programming Notes and Examples Issue Date: 01/02/13 320x240 Viewport 640x480 “Virtual” Display Figure 5-1: Viewport Inside a Virtual Display Page 25 S1D13705 X27A-G-002-02 ...

Page 118

... We require a total of 640 pixels. The horizontal display register will account for 320 pixels, this leaves 320 pixels for the Memory Address Offset register to account for. offset = pixels / pixels_per_word = 320 / 28h The Memory Address Offset register, REG[11h], will have to be set to 28h to satisfy the above condition. S1D13705 X27A-G-002-02 Memory Memory Address ...

Page 119

... Both panning and scrolling are performed by modifying the start address register. The start address registers in the S1D13705 are a word offset to the data to be displayed in the top left corner of a frame. Changing the start address by one means a change on the display of the number of pixels in one word ...

Page 120

... Table 5-1: Number of Pixels Panned Using Start Address Color Depth (bpp) Pixels per Word S1D13705 X27A-G-002-02 Start Addr Start Addr Bit 5 Bit 4 Bit 3 Start Addr Start Addr Bit 13 Bit 12 Bit 11 ...

Page 121

... The routine SetStartAddress() break up its long integer argument into three register values and store the values. void SetStartAddress(long SA) { REG[0C REG[0D] = (SA >> Reg[10] = (SA >> 16) & 0xFF this example code the notation REG[] refers to whatever mechanism is employed to read/write the registers. Programming Notes and Examples Issue Date: 01/02/13 & 0xFF; 8) & 0xFF; Page 29 S1D13705 X27A-G-002-02 ...

Page 122

... Step 2: Scroll up or down To scroll up. StartWord = GetStartAddress(); StartWord -= words_per_line; if (StartWord < 0) StartWord = 0; SetStartAddress(StartWord); To scroll down. StartWord = GetStartAddress(); StartWord += words_per_line; SetStartAddress(StartWord); } S1D13705 X27A-G-002-02 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/13 ...

Page 123

... The Split Screen feature of the S1D13705 allows a programmer to setup a display in such a manor. When correctly configured the programmer has only to update the main area on a regular basis ...

Page 124

... For instance, Screen 2 Start Address may point to offset zero of display memory while Screen 1 Start Address points to a location several thousand bytes higher. Screen 1 will still be shown first on the display. While not particularly useful even possible to set screen 1 and screen 2 to the same address. S1D13705 X27A-G-002-02 Bit 4 Bit 3 ...

Page 125

... Changing these registers by one will shift the display image pixels, depending on the current color depth. The S1D13705 does not support split screen operation in portrait mode. Screen 2 will never be used if portrait mode is selected. Refer to Table 5-1: “Number of Pixels Panned Using Start Address” to see the minimum ...

Page 126

... Screen 2 display data is coming from the very beginning of the display buffer. All there here is ensure that both the LSB and MSB of the Screen 2 Start Word Address registers are set to zero. S1D13705 X27A-G-002-02 located first (offset 0) in the display buffer followed immediately by im- age 1 ...

Page 127

... The S1D13705 performs automatic power sequencing in response to both software power save (REG[03h response to a hardware power save. One frame after a power save mode is set, the S1D13705 disables LCD power, and the LCD logic signals continue for one hundred and twenty seven frames allowing the LCD power supply to completely discharge ...

Page 128

... Disable the LCD logic by setting the software power save in REG[03h] or setting hardware power save via GPIO0. Keep in mind that after setting the power save mode there will be 127 frames before the LCD logic signals are disabled. S1D13705 X27A-G-002-02 Epson Research and Development ...

Page 129

... The benefits to using default portrait mode lies in the ability to use a slower input clock and in reduced power consumption. The following figure depicts the ways to envision memory layouts for the S1D13705 in default portrait mode. This example uses a 320x240 panel. Programming Notes and Examples ...

Page 130

... Figure 7-1: Relationship Between the Default Mode Screen Image and the Image Refreshed by S1D13705 From the programmers perspective the memory is laid out as shown on the left. The programmer accesses memory exactly as for a panel of with the dimensions of 240x320 setup to have a 256 pixel horizontal stride. The programmer sees memory addresses increasing from A-> ...

Page 131

... Figure 7-2: Relationship Between the Alternate Mode Screen Image and the Image Refreshed by S1D13705 From the programmers perspective the memory is laid out as shown on the left. The programmer accesses memory exactly as for a panel of with the dimensions of 240x320. ...

Page 132

... Select The portrait mode register contains several items for portrait mode support. The first is the Portrait Mode Enable bit. When this bit is “0” the S1D13705 is in landscape mode and the remainder of the settings in this register as well as the Line Byte Count in REG[1Ch] are ignored. Set this bit to “ ...

Page 133

... In portrait display mode the CLKI (input clock) is routed to the portrait section of the S1D13705 as CLK. From the CLK signal the MCLK value can be determined from table 8-8 of the Hardware Functional Specification, document number X27A-A-001-xx. If MCLK is determined to be less than or equal to 25 MHz then Portrait Mode Memory Clock Select may be enabled ...

Page 134

... Page 42 7.5 Limitations The only limitation to using portrait mode on the S1D13705 is that split screen operation is not supported. A comparison of the two portrait modes is as follows: Item Memory Requirements Clock Requirements Power Consumption Panning Performance S1D13705 X27A-G-002-02 Table 7-1: Default and Alternate Portrait Mode Comparison ...

Page 135

... The only item to keep in mind is that the count from the first pixel of one line to the first pixel of the next line (referred to as the “stride”) is 128 bytes. Programming Notes and Examples Issue Date: 01/02/13 Page 43 S1D13705 X27A-G-002-02 ...

Page 136

... Pixel Clock Select bits the PCLK value will be equal to CLK/2. These examples don’t use the Pixel Clock Select bits. The ability to divide the PCLK value down further than the default values was added to the S1D13705 to support hardware portrait mode on very small panels. ...

Page 137

... As this is the alternate portrait mode the power of two stride issue encountered with the default portrait mode is no longer an issue. The stride is the same as the portrait mode width. In this case 120 bytes. Programming Notes and Examples Issue Date: 01/02/13 PCLK FrameRate = ---------------------------------------------------------------------------------------- - HDP + HNDP VDP 16 000 000 ----------------------------- - 2 FrameRate = ------------------------------------------------------- 320 + 88 240 + 3 + VNDP = 80.69 X27A-G-002-02 Page 45 S1D13705 ...

Page 138

... In this case 281h (81h + 200h) will be written to the Screen 1 Start Address register set. Set Screen1 Display Start Word Address LSB (REG[0Ch]) to 81h and Screen1 Dis- play Start Word Address MSB (REG[0Dh]) to 02h. S1D13705 X27A-G-002- pixels. Epson Research and Development ...

Page 139

... It may be important for a program to identify between products at run time. Identification of the S1D13705 can be performed any time after the system has been powered up by reading REG[00h], the Revision Code register. The six most significant bits form the product identification code and the two least significant bits form the product revision ...

Page 140

... Using the HAL keeps sample code simpler, although some programmers may find the HAL functions to be limited in their scope, and may wish to program the S1D13705 without using the HAL. 9.2 Contents of the HAL_STRUCT The HAL_STRUCT below is contained in the file “ ...

Page 141

... Registers the S1D13705 parameters with the HAL, calls seInitHal if necessary. seRegisterDevice seRegisterDevice MUST be the first HAL function called by an application. Programs the S1D13705 for use with the default settings, calls seSetDisplayMode to do the seSetInit work, clears display memory. Note: either seSetInit or seSetDisplayMode must be called ...

Page 142

... Page 50 Function seSetReg Write a Byte value to the specified S1D13705 register seGetReg Read a Byte value from the specified S1D13705 register seWriteDisplayBytes Write one or more bytes to the display buffer at the specified offset seWriteDisplayWords Write one or more words to the display buffer at the specified offset ...

Page 143

... ERR_UNKNOWN_DEVICE - the HAL was unable to find an S1D13705. Configures the S1D13705 for operation. This function sets all the S1D13705 control registers to their default values. Initialization of the S1D13705 is a two step process to accommodate those programs (e.g. 13705PLAY.EXE) which do not initialize the S1D13705 on start-up. None ...

Page 144

... Description: Parameters: Return Value: None Example: S1D13705 X27A-G-002-02 Reads the S1D13705 revision code register to determine the chip product and revisions. The interpreted value is returned in pID. pId - pointer to an integer which will receive the controller ID. S1D13705 values returned in pID are: - ID_S1D13705_REV0 ...

Page 145

... S1D13705. This function reads the S1D13705 registers to determine the current color depth and returns the result in pBitsPerPixel. pBitsPerPixel - pointer to an integer to receive current color depth. ...

Page 146

... The S1D13705 registers must be initialized for this function to work correctly. On the PC platform this is simply a call to the C timing functions and is therefore independent of the register settings. ...

Page 147

... Return Value: ERR_OK - operation completed with no problems Programming Notes and Examples Issue Date: 01/02/13 This function call enables or disable the high performance bit of the S1D13705. When high performance is enabled then MClk equals PClk for all video display resolutions. In the high performance state CPU to video memory performance is improved at the cost of higher power consumption ...

Page 148

... The smallest surface screen 1 can display is one line. This is due to the way the S1D13705 operates. Setting Screen 1 Vertical Size to zero results in one line of screen 1 being displayed. The remainder of the display will be screen 2 image. Screen ...

Page 149

... X position in pixels y - new starting Y position in pixels ERR_HAL_BAD_ARG- there are several reasons for this return value: 1) WhichScreen is not SCREEN1 or SCREEN2. 2) the y argument is greater than the last available line less the screen height. Page 57 S1D13705 X27A-G-002-02 ...

Page 150

... Page 58 9.4.4 Register / Memory Access The Register/Memory Access functions provide access to the S1D13705 registers and display buffer through the HAL. int seGetReg(int Index, BYTE * pValue) Description: Parameters: Return Value: ERR_OK int seSetReg(int Index, BYTE Value) Description: Parameters: Return Value: ERR_OK int seReadDisplayByte(DWORD Offset, BYTE *pByte) ...

Page 151

... WORDS will have the same value. Offset - offset from start of the display buffer Value - WORD value to write Count - number of words to write - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Addr or if Addr plus Count is greater than 80 kb. Page 59 S1D13705 X27A-G-002-02 ...

Page 152

... ERR_HAL_BAD_ARG - if the value for Addr or if Addr plus Count is greater than 80 kb. This function sets on the S1D13705’s software selectable power save modes. PwrSaveMode - integer value specifying the desired power save mode. Acceptable values for PwrSaveMode are (software power save mode) in this mode registers and memory are read/writable ...

Page 153

... Currently seDrawLine() only draws horizontal and vertical lines. (x1, y1) - first endpoint of the line in pixels (x2, y2) - second endpoint of the line in pixels (see note below) Color - color to draw with. 'Color index into the LUT. Page 61 S1D13705 X27A-G-002-02 ...

Page 154

... Count) Description: Parameters: Return Value: ERR_OK - operation completed with no problems S1D13705 X27A-G-002-02 This routine draws and optionally fills a rectangular area of display buffer. The upper right corner is defined by x1,y1 and the lower right corner is defined by x2,y2. The color, defined by Color, applies both to the border and to the optional fill. ...

Page 155

... This routine reads one LUT entry from any index. A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue. The color information is stored in the four most significant bits of each byte. Index - index to LUT entry (0 to 255) pEntry - pointer to an array of three bytes Page 63 S1D13705 X27A-G-002-02 ...

Page 156

... Finally, you need to build the final application, linked together with the libraries described earlier. The following examples assume that you have a copy of the complete source code for the S1D13705 utilities, including the nmake makefiles, as well as a copy of the GNU Compiler v2.7-96q3a for Hitachi SH3. These are available on the World Wide Web at http://www ...

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... The Gnu compiler tools are pointed to by TOOLDIR. With nmake in your path run: nmake -fmakesh3.mk Programming Notes and Examples Issue Date: 01/02/13 Page 65 S1D13705 X27A-G-002-02 ...

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... Page 66 10 Sample Code Included in the sample code section are two examples of programing the S1D13705. The first sample uses the HAL to draw a red square, wait for user input then rotates to portrait mode and draws a blue square. The second sample code performs the same procedures but directly accesses the registers of the S1D13705 ...

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... Epson Research and Development Vancouver Design Center /* ** Get the product code to verify this is an S1D13705. */ seGetId(&ChipId); if (ID_S1D13705_Rev1 != ChipId) { printf("\nERROR: Did not detect an S1D13705."); exit(1 Initialize the S1D13705. ** This step programs the registers with values taken from ** the HalInfo struct in appcfg.h. ...

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... This second sample demonstrates exactly the same sequence as the first howerver the HAL is not used, all manipulation is done by directly accessing the registers. /* **=========================================================================== ** SAMPLE2.C - Sample code demonstating a direct access of the S1D13705. **------------------------------------------------------------------------- ** Created 1998, Vancouver Design Centre ** Copyright (c) 1998, 1999 Epson Research and Development, Inc. ...

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... BitsPerPixel = 8; int Width = 320; int Height = 240; int OffsetBytes; int rc Get a linear address we can use in our code to access the S1D13705. ** This is only needed to access the S1D13705 on the ISA eval board. Programming Notes and Examples Issue Date: 01/02/ ...

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... IntelGetLinAddressW32(0xF00000, &dwLinearAddress printf("Error getting linear address"); return; } p13705 = (PBYTE)dwLinearAddress; pRegs = p13705 + 0x1FFE0 Check the revision code. Exit if we don't find an S1D13705 (0x24 != *pRegs) { printf("Didn't find an S1D13705"); return Initialize the chip - after intialization the display will be ** setup for landscape use. ...

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... Used for setting memory to a width greater than the ** ** */ Programming Notes and Examples Issue Date: 01/02/13 desired frame rate according to: PCLK (HDP + HNDP) * (VDP + VNDP) achieve the desired frame rate. display size. Usually set to 0 during initialization and programmed to desired value later. Page 71 = (0+ pels S1D13705 X27A-G-002-02 ...

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... Register 15h - Look-Up Table Address ** - Set start RGB sequencing at the first LUT entry. */ SET_REG(0x15, 0x00); S1D13705 X27A-G-002-02 for split screen operation. Normally it is set to maximum value. pins low should GPIO be set as outputs. system may require. Epson Research and Development ...

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... Draw a pixel with LUT color 4 */ pMem++; } } /* ** Wait for the user to press a key before continuing. */ printf("Press any key to continue"); getch(); /* ** Set and use PORTRAIT mode Programming Notes and Examples Issue Date: 01/02/13 Page 73 S1D13705 X27A-G-002-02 ...

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... Set the memory pointer at the start of each line. ** Pointer = MEM_OFFSET + (Y * Line_Width * BPP / BPP / 8) ** NOTICE: as this is default portrait mode, the width is a power ** ** S1D13705 X27A-G-002-02 of two. In this case, we use a value of 256 pixels for our calculations instead of the panel dimension of 240. Epson Research and Development Vancouver Design Center ...

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... The CREATE_NEW flag is not necessary hDriver = CreateFile("\\\\.\\S1D13x0x.VXD", 0,0, (hDriver == INVALID_HANDLE_VALUE) return - From now on, the code is common for Win95 & WinNT */ if (physaddr == 0) Programming Notes and Examples Issue Date: 01/02/13 /* Draw a pixel in LUT color NULL, OPEN_EXISTING,FILE_ATTRIBUTE_NORMAL, NULL); CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); Page 75 S1D13705 X27A-G-002-02 ...

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... Close the handle. ** This will dynamically UNLOAD the Virtual Device for Win95. */ CloseHandle(hDriver); if (rc) return 0; return -1; } S1D13705 X27A-G-002-02 &Arr[0 sizeof(ULONG), &retVal, sizeof(ULONG), &cbReturned, NULL); Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/13 ...

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... Header Files The header files included here are the required for the HAL sample to compile correctly. /* **=========================================================================== ** HAL.H - Header file for use with programs written to use the S1D13705 HAL. **--------------------------------------------------------------------------- ** Created 1998, Vancouver Design Centre ** Copyright (c) 1998, 1999 Epson Research and Development, Inc. ...

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... DPFL(exp) printf(#exp " = %x\n", exp) #else #define DPF(exp) ((void)0) #define DPF1(exp) ((void)0) #define DPFL(exp) ((void)0) #endif /*-------------------------------------------------------------------------*/ enum { ERR_OK = 0, */ S1D13705 X27A-G-002-02 Epson Research and Development " #exp2 "=%d\n", exp1, exp2 error, call was successful. Programming Notes and Examples Vancouver Design Center Issue Date: 01/02/13 ...

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... Reg[MAX_REG + 1]; DWORD dwClkI; DWORD dwDispMem;/* */ WORD wFrameRate;/* */ } HAL_STRUCT; typedef HAL_STRUCT * PHAL_STRUCT; #ifdef INTEL_16BIT typedef HAL_STRUCT far * LPHAL_STRUCT; #else typedef HAL_STRUCT * LPHAL_STRUCT; Programming Notes and Examples Issue Date: 01/02/13 /* General purpose failure 256 Input Clock Frequency (in kHz) */ Page 79 S1D13705 X27A-G-002-02 ...

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... DWORD color, BOOL Solidfill ); /*------------------------------ Color ------------------------------------*/ int seSetLut( BYTE *pLut ); int seGetLut( BYTE *pLut ); int seSetLutEntry( int index, BYTE *pEntry ); int seGetLutEntry( int index, BYTE *pEntry ); #endif /* _HAL_H_ */ S1D13705 X27A-G-002-02 FUNCTION PROTO-TYPES Epson Research and Development Vancouver Design Center */ Programming Notes and Examples ...

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... Programming Notes and Examples Issue Date: 01/02/ 0x27, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ClkI (kHz Display Address */ /* Panel Frame Rate (Hz 0x00, 0x00, 0x00, 0x00, X27A-G-002-02 Page 81 S1D13705 ...

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... REG_GPIO_CONFIG #define REG_GPIO_STATUS #define REG_SCRATCHPAD #define REG_PORTRAIT_MODE #define REG_LINE_BYTE_COUNT #define REG_NOT_PRESENT_1 /* ** WARNING!!! MAX_REG must be the last available register!!! */ #define MAX_REG #endif /* __HAL_REGS_H__ */ S1D13705 X27A-G-002-02 Epson Research and Development All rights reserved. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 ...

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... CTL_CODE( SED_TYPE, 0x900, METHOD_BUFFERED, FILE_ANY_ACCESS) #define IOCTL_SED_MAP_PCI_BOARD \ CTL_CODE( SED_TYPE, 0x901, METHOD_BUFFERED, FILE_ANY_ACCESS) #define IOCTL_SED_MAP_PHYSICAL_MEMORY \ CTL_CODE( SED_TYPE, 0x902, METHOD_BUFFERED, FILE_ANY_ACCESS) #define IOCTL_SED_UNMAP_LINEAR_MEMORY \ CTL_CODE( SED_TYPE, 0x903, METHOD_BUFFERED, FILE_ANY_ACCESS) Programming Notes and Examples Issue Date: 01/02/13 The IOCTL code contains a command Page 83 S1D13705 X27A-G-002-02 ...

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... Page 84 S1D13705 X27A-G-002-02 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/13 ...

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... Line Byte Count Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 0 Notes 1 These bits are used to identify the S1D13705 at power on / reset addresses are relative to the beginning of display memory. 3 Gray Shade/Color Mode Selection Bit 0 Color/Mono Bit-Per-Pixel Bit 1 Bit-Per-Pixel Bit 0 REG[01] bit 5 REG[02] bit 7 ...

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... S1D13705 Register Summary Page 2 X27A-R-001-03 01/02/13 ...

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... S1D13705 Embedded Memory LCD Controller 13705CFG Configuration Program Document Number: X27A-B-001-02 Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice.You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...

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... Page 2 S1D13705 X27A-B-001-02 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center 13705CFG Configuration Program Issue Date: 01/03/29 ...

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... Epson Research and Development Vancouver Design Center 13705CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 S1D13705 Supported Evaluation Platforms . . . . . . . . . . . . . . . . . . . . . . 5 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13705CFG Configuration Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Preferences Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clocks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Panel Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Panel Power Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Registers Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13705CFG Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Open... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Save As... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Configure Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Export . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Enable Tooltips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ERD on the Web ...

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... Page 4 S1D13705 X27A-B-001-02 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center 13705CFG Configuration Program Issue Date: 01/03/29 ...

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... Windows® 9x/ME/NT/2000 program that calculates register values for a user defined S1D13705 configuration. The configuration information can be used to directly alter the operating characteristics of the S1D13705 utilities or any program built with the Hardware Abstraction Layer (HAL) library. Alternatively, the configuration information can be saved in a variety of text file formats for use in other applications ...

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... Page 6 Installation Create a directory for 13705cfg.exe and the S1D13705 utilities. Copy the files 13705cfg.exe and panels.def to that directory. Panels.def contains configuration infor- mation for a number of panels and must reside in the same directory as 13705cfg.exe. Usage 13705CFG can be started from the Windows desktop or from a Windows command prompt ...

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... Configuration Tabs 13705CFG provides a series of tabs which can be selected at the top of the main window. Each tab allows the configuration of a specific aspect of S1D13705 operation. The tabs are labeled “General”, “Preference”, “Clocks”, “Panel”, “Panel Power”, and “ ...

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... PCI interface and the decode addresses are determined by the system BIOS during boot-up. If using the S1D13705 Evaluation Board on a PCI based platform, both Windows and the S1D13XXX device driver must be installed. For further information on the S1D13XXX device driver, see the S1D13XXX Windows 32-bit Windows Device Driver Installation Guide, document number X00A-E-003-xx ...

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... Alternative Mode 13705CFG Configuration Program Issue Date: 01/03/29 Sets the initial color depth on the LCD panel. The S1D13705 SwivelView feature is capable of rotating the image displayed on an LCD panel 90° counter-clockwise direction. This sets the initial orien- tation of the panel. When this box is checked SwivelView is enabled and the LCD display is rotated 90° ...

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... CLKI The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals. For further information regarding clocking and clock sources, refer to the S1D13705 Hardware Functional Specification, document number X27A-A-001-xx. Note Options for LCD frame rates are limited to ranges determined by the clock values. Also, changing clock values may modify or invalidate Panel settings ...

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... Epson Research and Development Vancouver Design Center The S1D13705 uses one clock input known as CLKI. The pixel clock (PCLK) and the memory clock (MCLK) are both derived directly from CLKI. CLKI PCLK Source Divide Timing MCLK Source Divide Timing 13705CFG Configuration Program Issue Date: 01/03/29 This setting determines the frequency of CLKI ...

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... Panel Tab Format 2 Panel Data Width Panel Type Panel Type Panel Dimensions TFT/FPLINE The S1D13705 supports many panel types. This tab allows configuration of most panel settings such as panel dimensions, type and timings. Panel Type S1D13705 X27A-B-001-02 FPLINE Dual Panel Panel Color ...

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... Issue Date: 01/03/29 Selects color STN panel format 2. This option is specif- ically for configuring 8-bit color STN panels. See the S1D13705 Hardware Functional Specification, document number X27A-A-001-xx, for description of format 1 / format 2 data formats. Most new panels use the format 2 data format. ...

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... FPFRAME pulse. This settings is only available when the selected panel type is TFT. Refer to S1D13705 Hardware Functional Specifi- cation, document number X27A-A-001-xx, for a complete description of the FPFRAME pulse settings. 13705CFG uses a file (panels.def) which lists various panel manufacturers recommended settings ...

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... GPIO0 is enabled. When this box is unchecked, the Hardware Power Save function is not available. This setting controls the time delay between when the LCD panel is powered-off and when the S1D13705 control signals are turned off. This setting must be configured according to the specification for the panel being used ...

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... X27A-B-001-02 Epson Research and Development This setting controls the time delay between when the S1D13705 control signals are turned on and the LCD panel is powered-on. This setting must be configured according to the specification for the panel being used. This value is only used by Epson evaluation software designed for the S5U13705B00C evaluation board ...

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... Epson Research and Development Vancouver Design Center Registers Tab The Registers tab allows viewing and direct editing the S1D13705 register values. Scroll up and down the list of registers and view their configured values based on the settings in the previous tabs. Individual register settings may be changed by double- clicking on the register in the listing ...

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... This may be used to quickly arrive at a starting point for register configuration. The only requirement is that the file being opened must contain a valid S1D13705 HAL library information block. 13705CFG supports a variety of executable file formats. Select the file type(s) 13705CFG should display in the Files of Type drop-down list and then select the filename from the list and click on the Open button ...

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... BMP60Hz.EXE, BMP72Hz.EXE, BMP75Hz.EXE where only the frame rate changes in each of these files). Note When “Save As” is selected then an exact duplicate of the file as opened by the “Open” option is created containing the new configuration information. 13705CFG Configuration Program Issue Date: 01/03/29 Page 19 S1D13705 X27A-B-001-02 ...

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... MPC and IDP based programs at the same time for a new panel type, the physical addresses for each are retained. This feature is primarily intended for the test lab where multiple hardware configurations exist and are being tested. S1D13705 X27A-B-001-02 Epson Research and Development ...

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... Notepad with a copy of the configuration file about to be saved. When the C Header File for S1D13705 WinCE Drivers option is selected as the export type, additional options are available and can be selected by clicking on the Options button. The options dialog appears as: ...

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... Comments • On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13705 (i.e. Selecting TFT or STN on the Panel tab enables/disables options specific to the panel type). • The file panels.def is a text file containing operational specifications for several supported, and tested, panels. This file can be edited with any text editor. • ...

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